CXD2458 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2458

Timing Generator for Color LCD Panels

Sony Semiconductor 

CXD2458AR

AFC Circuit (PLL Method)

The CXD2458AR employs the PLL method in order to achieve phase synchronization with the input sync

signal.

The PLL circuit phase comparator and frequency division counter are built in, and a fully synchronized AFC

circuit is comprised by connecting an external VCO circuit and LPF.

PLL errors are detected at the following timing.

The phase comparison output of the entire bottom of XHD or the horizontal sync signal of composite SYNC

and the internal H counter becomes RPD. RPD output is converted to DC error with the lag-lead filter (LPF),

and then it changes the varicap capacitance to stabilize the oscillating frequency at 702fh in the

LCX005BK/BKB and LCX024AK, and 1050fh in the LCX009AK/AKB and LCX027AK.

This PLL circuit is adjusted by setting the RPD transition point so that it sets in the center of the window (XHD

or horizontal sync signal of composite SYNC) as shown in the figure below.

XHD or horizontal sync signal of

composite SYNC

4.7µs

RPD

WL = WH

WL

WH

AC Driving for No Signal

HST1/2, HCK1/2, FRP, VCK1/2, XCLP, VST, HD, VD, SH1/2/3/4 and EN are made to run freely so that the

LCD panel is AC driven even when there are no input sync signals (XHD/XVD and composite SYNC).

During this time, the horizontal sync separation circuit stops and the PLL internal frequency division counter is

made to run freely. At the same time, the auxiliary V counter is used to create the reference pulse for

generating the free running VD and VST because the vertical sync separation circuit is also stopped.

The cycle of this V counter is set to 269H for NTSC and 321H for PAL. However, when there is no XVD

(VSYNC) input for 301H (NTSC) and 360H (PAL), the no signal state is assumed and the free running VD and

VST pulses are generated from the next field.

RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing phase

errors due to phase comparison.

System Clear (XCLR)

The entire logic is initialized by setting XCLR = L. Be sure to perform this operation during power-on and after

changing the STBY pin from L to H. When this function is activated the outputs (XCLP, HD, FRP, VST, VD,

CLR, EN, HST1/2, HCK1/2, SH1/2/3/4, VCK1/2, FLDO, SBLK and BLK) go to L.

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