CXD1261 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD1261

Sync Signal, Timing Signal Generator for CCD Cameras

Sony Semiconductor 

CXD1261AR

2-2. When using parallel input (PS = High)

Shutter speed table

Only the high-speed shutter is used when using parallel input (During frame accumulation, low-speed shutter

does not operate normally.)

D1 ENB ED0 ED1 ED2

X

L

X

X

X

L

H

H

H

H

H

H

H

H

H

L

H

L

H

H

H

H

L

H

H

X

H

H

L

H

X

H

L

L

H

X

H

H

H

L

X

H

L

H

L

X

H

H

L

L

X

H

L

L

L

Shutter speed

Shutter off ∗1

1/60 (s) ∗2

1/50 (s) ∗2

1/100 (s)

1/120 (s)

1/250 (s)

1/500 (s)

1/1000 (s)

1/2000 (s)

1/4000 (s)

1/10000 (s)

∗1 XSUB (shutter pulse) is not generated.

∗2 Accumulation time is as follows regardless

of field accumulation/frame accumulation.

D1 = Low (EIA), 1/60 (s)

D2 = High (CCIR), 1/50 (s)

(Pseudo field readout during frame

accumulation.)

2-3. When using serial input (PS = Low)

The following four modes can be selected according to the combination of serial data SMD1 and SMD2.

(During frame accumulation, low-speed shutter does not operate normally.)

Shutter mode

Mode

Flickerless

High-speed shutter Low-speed shutter

No shutter

SMD1

L

L

H

H

SMD2

L

H

L

H

• Flickerless:

Eliminates flicker resulting from the frequency of fluorescent light

• High-speed shutter: Higher speed shutter than 1/60 (EIA), 1/50 (CCIR)

• Low-speed shutter: Lower speed shutter than 1/60 (EIA), 1/50 (CCIR)

(Does not operate normally during frame accumulation.)

• No shutter:

No shutter operation

<Input timing when using serial input>

ED1 (CLK)

ED2 (DATA)

ED0 (STB)

D0 D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy

The data on ED2 is latched in the register at the rising edge of ED1 and is then taken in internally while ED0 is

low.

–9–

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