CXA3562AR 데이터 시트보기 (PDF) - Sony Semiconductor

부품명

상세내역

일치하는 목록

CXA3562AR

LCD Driver

Sony Semiconductor 

CXA3562AR

Description of Operation

The flow of internal operations is described below.

The digital signals input to D_A9 to D_A0 and D_B9 to D_B0 are internally D/A converted into approximately

1.5V (at VREF_I: 3.2V) analog signals. After that, the signal that has been demultiplexed into 12 phases is

amplified by a factor of three times, inverted at the signal center potential according to FRP, and output.

The output level relative to the digital input changes according to the following settings.

A: SIG_OFST voltage

B: VREF_I voltage

VCC

C: SIG.C voltage

B

1023

512

0

Digital IN

A

Signal Center

A

C

B

SH_OUT

GND

1. Digital input block

The CXA3562AR can be set to single input from only the A port or parallel input from both the A and B ports,

and port switching by right/left inversion is also possible in parallel input mode. This makes it possible to

support various systems.

In single input mode, the signal is internally demultiplexed to 2-parallel format and input to the D/A converter.

2. D/A converter block

The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input

from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a

maximum 1.5Vp-p with respect to input data of 000h to 3FFh.

3. Sample-and-hold (S/H) block

The odd-numbered and even-numbered D/A converter outputs are input to the odd-numbered and even-

numbered sample-and-hold blocks, respectively. The signals are converted from time series signals into 6-phase

cyclic parallel signals by the sample-and-hold group which is appropriately controlled by the internal timing

generator. For forward scan, the signals are output in the ascending order of SH_OUT1, SH_OUT2, SH_OUT3

... SH_OUT12. For reverse scan, this order is inverted and the signals are output in descending order. Connect

the signals to the LCD panel according to the order used. The timing of each sample-and-hold pulse is shown

on the following pages. These pulses are not output and are used only inside the IC.

– 11 –

Share Link: