CXA2019 데이터 시트보기 (PDF) - Sony Semiconductor
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CXA2019 Datasheet PDF : 30 Pages
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CXA2019AQ
Description of Operation
1. Sync System
The video signals (standard input level: 2Vp-p) input to Pins 38 and 39 are sync separated by the horizontal
and vertical sync separation circuits.
The resulting horizontal sync signal and the signal obtained by frequency dividing the 32fH-VCO output
using the ceramic oscillator (frequency 500kHz or 503.5kHz) by 32 are phase compared, the AFC loop is
constructed, and an H pulse (HTIM) synchronized with the H sync is output from Pin 15.
The vertical sync signal is sent to the V countdown block where the most appropriate window processing is
performed to obtain V sync timing information which resets the counter. A V pulse (VTIM) synchronized
with the V sync is output from Pin 14. In addition, BGP, HBLK and VBLK are output from Pin 16 as SCP
(sand castle pulse).
2. Y System
There are two input systems.
Composite video input (2Vp-p) → 1 system
Y/C separation input (2Vp-p) → 1 system
The Y signal (specified input level: 2Vp-p) input to Pin 34 passes through the subcontrast control, chroma
trap, delay line, sharpness control, clamp and auto pedestal circuits, is gain adjusted by the YDRIVE circuit
and is then output.
The CXA2019AQ has a built-in chroma trap, enabling the video signal to be input directly. The trap
frequency is automatically adjusted inside the IC. However, the trap frequency is affected by variations
among the ICs, so fine adjustment through the I2C bus may be required.
Because the f0 of the filter is not specified when the color killer function is operating, turn the trap OFF if
there are any difficulties.
The Y signal delay time can be varied in approximately 60ns increments through the I2C bus register
(DELAY). In addition, when the C system TOT is ON, the Y signal delay time is increased by approximately
140ns to cope with the increase in the C system delay time caused by the TOT filter.
The sharpness control is a delay line type and the sharpness f0 can be switched to 1.5MHz or 3MHz.
3. C System
The CVBS or chroma signal (specified input level: burst level of 570mVp-p) selected by the internal video
switch passes through the ACC, TOT, chroma amplifier and demodulation circuits, is demodulated into the
R-Y and B-Y color difference signals, and is then inversed and output from Pins 23 and 24. However,
during NTSC the signals are 6dB amplified by the internal DET switch and gain adjusted by the COLOR
circuit. During PAL the signals are 6dB amplified by the 1H delay line, input to Pins 21 and 22, and gain
adjusted by the COLOR circuit. Signals that have passed through the 1H delay line can also be input to the
COLOR circuit during NTSC by using the I2C bus register (EXT COLOR). This provides comb filter effects.
In addition, the color system (NTSC/PAL) and the subcarrier frequency (3.58MHz/4.43MHz) are
automatically identified according to the input chroma signal, and the internal VCO and demodulation
circuit, etc., are adjusted automatically. Furthermore, SECAM signals can also be automatically identified
by connecting an external SECAM decoder to Pin 30. In this case, Pins 23 and 24 and the SECAM decoder
color difference output are linked together directly, and one side goes to high impedance and the other side
goes to low impedance according to the input chroma signal, and then they are input to the external 1H
delay line.
System identification can be set to automatic or forced mode by the I2C bus register. The color system is
output to the status register.
The pedestal levels of the U and V color difference signals are clamped by UPED and VPED, respectively,
and then these signals are output. However, the DC of the video portion can be controlled by the I2C bus
register, allowing the offset to be adjusted at the PINP processor input.
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