CDB4226 데이터 시트보기 (PDF) - Cirrus Logic

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CDB4226

Surround Sound Codec

Cirrus Logic 

CS4226

SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: logic 0 = DGND, logic 1 =

VD+, CL = 30 pF)

Parameter

Symbol

Min

I2C® Mode (SPI/I2C = 1)

SCL Clock Frequency

fscl

-

Bus Free Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low Time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 14)

thdd

0

SDA Setup Time to SCL Rising

tsud

250

Rise Time of Both SDA and SCL Lines

tr

Fall Time of Both SDA and SCL Lines

tf

Setup Time for Stop Condition

tsusp

4.7

Max

Units

100

kHz

µs

µs

µs

µs

µs

µs

ns

1

µs

300

ns

µs

Notes: 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL

S/PDIF RECEIVER CHARACTERISTICS (RX1, RX2, RX3, RX4 pins only)

Parameter

Input Resistance

Input Voltage

Input Hysteresis

Input Sample Frequency

CLKOUT Jitter

CLKOUT Duty Cycle (high time/cycle time)

Symbol Min Typ

(Note 15)

ZN

VTH

VHYST

FS

-

10

200

-

-

50

30

-

-

200

(Note 16)

40

50

Max Units

-

kΩ

-

mVpp

-

mV

50

kHz

-

ps RMS

60

%

Notes: 15. CLKOUT Jitter is for 256×FS selected as output frequency measured from falling edge to falling edge.

Jitter is greater for 384×Fs and 512×Fs as selected output frequency.

16. For CLKOUT frequency equal to 1×Fs, 384×Fs, and 512×Fs. See Master Clock Output section.

DIGITAL CHARACTERISTICS

Parameter

High-level Input Voltage

(except RX1)

Low-level Input Voltage

(except RX1)

High-level Output Voltage at I0 = -2.0 mA

Low-level Output Voltage at I0 = 2.0 mA

Input Leakage Current

(Digital Inputs)

Output Leakage Current (High-Impedance Digital Outputs)

Symbol

VIH

VIL

VOH

VOL

Min

2.8

-0.3

(VD+)-1.0

-

-

-

Typ Max Units

- (VD+)+0.3 V

-

0.8

V

-

-

V

-

0.4

V

-

10

µA

-

10

µA

DS188F4

9

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