CDB4221 데이터 시트보기 (PDF) - Cirrus Logic

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CDB4221

24-Bit Stereo Audio Codec with 3V Interface

Cirrus Logic 

CS4220 CS4221

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221)

(TA = 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 30 pF)

Parameter

SPI Mode (SPI/I2C = 0)

Symbol

Min

Max

Unit

CCLK Clock Frequency

RST rising edge to CS falling

CCLK edge to CS falling

CS High Time between transmissions

CS falling to CCLK edge

CCLK Low Time

CCLK High Time

CDIN to CCLK rising setup time

CCLK rising to DATA hold time

Rise time of CCLK and CDIN

Fall time of CCLK and CDIN

fsck

-

(Note 11)

tsrs

41

(Note 12)

tspi

500

tcsh

1.0

tcss

20

tscl

66

tsch

66

tdsu

40

(Note 13)

tdh

15

(Note 14)

tr2

-

(Note 14)

tf2

-

6

MHz

-

µs

-

ns

-

µs

-

ns

-

ns

-

ns

-

ns

-

ns

100

ns

100

ns

Notes: 11. Not tested but guaranteed by design.

12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

13. Data must be held for sufficient time to bridge the transition time of CCLK.

14. For FSCK < 1 MHz.

RST

t srs

CS

CCLK

CDIN

t spi tcss

t scl t sch

t r2

t f2

t dsu t dh

Figure 2. SPI Control Port Timing

t csh

8

DS284PP3

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