CMX882 데이터 시트보기 (PDF) - CML Microsystems Plc

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CMX882

FRS Signalling Processor

CML Microsystems Plc 

FRS Signalling Processor

CMX882

Block 1 – XTCSS and In-band tone Setup:

Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

P1.0 1 1 0 1

Audio band Tx level

Emph

P1.1 0

1

0

1

XTCSS

tone length

Audio band detect threshold

In-band tone detect

bandwidth

P1.2 0 1 0 1 0

Programmable In-band Tone 0

P1.3 0 1 0 1 0

Programmable In-band Tone 1

P1.4 0 1 0 1 0

Programmable In-band Tone 2

P1.5 0 1 0 1 0

Programmable In-band Tone 3

Block 2 – CTCSS and DCS Setup:

Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

P2.0 1 1 1 0

CTCSS and DCS Tx level

P2.1 0

1

1

0

DCS

24

0

CTCSS and DCS detect threshold

CTCSS detect

bandwidth

P2.2 0 1 1 0

DCS Code bits 11 – 0

P2.3 0 1 1 0

DCS Code bits 23/22 – 12

P2.4 0 1 1 0

Sub-audio drop out

0

time

Block 3 – Reserved. Do not use.

Block 4 – Gain and Offset Setup:

Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

P4.0 1 0

Fine Input Gain

P4.1 0 0

Reserved - set to '0'

P4.2 0 0

Fine Output Gain 1

P4.3 0 0

Fine Output Gain 2

P4.4 0 0

Output 1 Offset Control

P4.5 0 0

Output 2 Offset Control

P4.6 0 0

Ramp Rate Control

P4.7 0 0

Limiter Setting (all 1's = Vbias +/- 0.5 Vdd)

P4.8 0 0

Special Programming Register (Production Test Only)

 2004 CML Microsystems Plc

51

D/882/7

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