CDP6402 데이터 시트보기 (PDF) - Harris Semiconductor
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CDP6402 Datasheet PDF : 12 Pages
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CDP6402, CDP6402C
Dynamic Electrical Specifications at TA = -40oC to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF
LIMITS
CDP6402
CDP6402C
(NOTE 1)
PARAMETERS
VDD
(NOTE 2) (NOTE 3) (NOTE 2) (NOTE 3)
(V)
TYP
MAX
TYP
MAX
UNITS
RECEIVER TIMING (See Figure 8)
Minimum Clock Period (RRC)
tCC
5
250
310
250
310
ns
10
125
155
-
-
ns
Minimum Pulse Width
Clock Low Level
tCL
5
100
125
100
125
ns
10
75
100
-
-
ns
Clock High Level
tCH
5
100
125
100
125
ns
10
75
100
-
-
ns
Data Received Reset
tDD
5
50
75
50
75
ns
10
25
40
-
-
ns
Minimum Setup Time
Data Start Bit to Clock
tDC
5
100
150
100
150
ns
10
50
75
-
-
ns
Propagation Delay Time
Data Received Reset to
Data Received
tDDA
5
150
250
150
250
ns
10
75
125
-
-
ns
Clock to Data Valid
tCDV
5
275
400
275
400
ns
10
110
175
-
-
ns
Clock to DR
tCDA
5
275
400
275
400
ns
10
110
175
-
-
ns
Clock to Overrun Error
tCOE
5
275
400
275
400
ns
10
100
150
-
-
ns
Clock to Parity Error
tCPE
5
240
375
240
375
ns
10
120
17
-
-
ns
Clock to Framing Error
tCFE
5
200
300
200
300
ns
10
100
150
-
-
ns
NOTES:
1. All measurements are made at the 50% point of the transition except three-state measurements.
2. Typical values for TA = 25oC and nominal VDD.
3. Maximum limits of minimum characteristics are the values above which all devices function.
5-85
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