CDP1853 데이터 시트보기 (PDF) - Intersil

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CDP1853

N-Bit 1 of 8 Decoder

Intersil 

Timing Diagrams

CDP1853, CDP1853C

tEO

tEO

CE

OUTPUT

FIGURE 2A. CE TO OUTPUT (0-7) DELAY TIME

tNO

tNO

N

OUTPUT

FIGURE 2B. N LINES TO OUTPUT (0-7) DELAY TIME

CLOCK A

tCACA

tAO

CLOCK B

tCBCB

tBO

OUTPUT

OUTPUT

FIGURE 2C. CLOCK A TO OUTPUT (0-7) DELAY TIME

FIGURE 2D. CLOCK B TO OUTPUT (0-7) DELAY TIME

FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS

TPA

TPB

CE

EN

(NOTE 1)

OUTPUT

NOTE 1. OUTPUT ENABLED WHEN EN = HIGH

INTERNAL SIGNAL SHOWN FOR

REFERENCE ONLY (SEE FIGURE 1)

FIGURE 3. TIMING DIAGRAM

A

B

C

CHIP ENABLE

VDD

N0

N1

N2

CE

CLOCK B

CLOCK A

OUT 0

OUT 1

OUT 2

OUT 3

OUT 4

OUT 5

OUT 6

OUT 7

FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER

4-38

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