Figure 5: Byte Write Sequence
CAT24AA01, CAT24AA02
BUS ACTIVITY:
MASTER
S
T
A
R
SLAVE
ADDRESS
T
S
ADDRESS
BYTE
a7 ÷ a0
DATA
BYTE
S
T
O
d7 ÷ d0
P
P
SLAVE
A
A
A
C
C
C
K
K
K
Figure 6: Write Cycle Timing
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7: Page Write Sequence
BUS ACTIVITY: S
T
A
MASTER R
T
S
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
SLAVE
A
A
A
A
C
C
C
C
K
K
K
K
n =1
x ≤ 15
DATA
S
BYTE
T
n+x
O
P
P
A
C
K
Figure 8: WP Timing
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
8
SCL
SDA
a7
a0
d7
d0
tSU:WP
WP
tHD:WP
© Catalyst Semiconductor, Inc.
7
Characteristics subject to change without notice
Doc. No. MD-1120 Rev. B