ACE9050D 데이터 시트보기 (PDF) - Mitel Networks
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ACE9050D Datasheet PDF : 52 Pages
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ACE9050
SYNTHDATA
SYNTHCLK
DTFG
LATCH0
LATCH1
LATCH3
EMUL
AS
R/W
D [7:0]
A [7:0]
A [13:8]
A [15:14]
BA [17:14]
CSE2N
CSEPN
72
SYNTHDATA
ONRAD
73
SYNTHCLK ACE
SINTSLEEP
C1008
82
DTFG
SERIAL IRQSEND
INTERFACE IRQREC
80
LATCH0
LSICOM0
78
LATCH1
LSICOM1
LSICOM2
75
LATCH3
LSICOM3
LSICOM4
LATCH2
LSICOM5
LSICOM6
MRI IRW ID[7:0] STR_WIDTH
TO
MUX #2
TO 6303
83
5
95
18-25
8
40,39,35-30 8
46-41
6
92,93
2
BUS INTERFACE
EMUL ONLY
EMUL IP
IRW
EMUL DATA/AD ID7:0
AD15:0
EMUL IP
EMUL IP
PORT3[6]
PORT4[7]
}INTERRUPTS
REFER TO TEXT
FOR INDIVIDUAL
BIT FUNCTIONS
O/P IN EMULATION
DATA
INTERNAL ADDRESS
50-47
4
29
28
MEMORY BANK
SWITCHING EPROM
BANK_SEL
MRI IRW ID[4:0] AD[15:14]
PULSE WIDTH MODULATOR
DAC1
PWM #1
DAC2
PWM #2
MRI IRW ID[7:0]
INTERNAL PORTS
PORT3 [7:0]
PORT3
PORT3
PORT4 [7:0] PORT4
PORT4
PORT5 [7:0] PORT5
PORT5
MRI IRW ID[7:0] LVN1
ID [7:0]
RAM AD [12:0]
6016 BYTES
(IRAM)
IRW
IRAM
ROM
ID [7:0]
512 BYTES AD [8:0]
(IROM)
IRW
BOOT BLOCK IROM
OUT2 [1]
PORT5 [0]
CONTROL PORT5 [5:4]
OUT2 [2]
LATCH2
MUX #1
MUX CONTROL
MUX #2
98 OUTP2 [1]/
PWM1
81
OUTP2 [2]/
PWM2/
LATCH2
EXTERNAL PORTS
O/P PORT2
OUT_PORT2
OUT2 [7]
OUT2 [6]
OUT2 [5:3]
OUT2 [2]
OUT2 [1]
OUT2 [0]
I/P PORT1
IN_PORT1
INP1 [7]
INP1 [6]
INP1 [4:2]
INP1 [1:0]
IRQE
EXT. INTERRUPTS
IRQPRT4-RESET
IRQPRT5-MASK
IRQPRT6-READ
KEYPORT/CHIP ID
KEYP R/W TO PORT
KPOT O/P TRISTATE
MRI IRW ID[7:0]
79 OUTP2 [7]
76 OUTP2 [6]
NOT BONDED
TO MUX #2
TO MUX #1
TO CPUCL PIN
POWERDET
SERV
54, 53, 52
3
INP1 [4:2]
2
70, 71 INRQ [1:0]
5
59-55 KPO [4:0]
4
66-69 KPI [3:0]
OEN
WEN
BAR
ICN (EMUL)
AFC/RXDATA
VDD
VDDM
VSS
SERV
MRN
RXCD
TXPOW
IN_PORT1
OUT_PORT2
26
ACE9050
REGISTER
SELECTS
IRQPRT4
DECODER IRQPRT5
IRAM
27
EPROM
MEMORY
SELECTS
IROM
IROME
PORT4 [1]
MRI IRW AD[15:0] SLEEP
PORT3 [1]
BEEP ALARM RING
GENERATOR (BAR)
96
BAR
BARENABLE
BARHIGH
BARLOW
MRI ID[7:0] CLKBUS
TO 6303
126kHz
77
ICN IFC COUNTER
IFFREQ (2432/256) PORT3 [0]
60
STIFCN (START/RESET) PORT3 [5]
11, 64, 65, 68
38
10, 17, 36, 37, 86, 87
54kHz/450kHz
INP1 [6]
WATCHDOG AND ATO
74
REWD
91
MASTER RESET WATCHDOG
MRI
AND
LVN1
RESET LOGIC
ISDA ISCL
AD15:O
6303
PORT1 [7:0]
ID7:0
MICROPROCESSOR
IRW READ/WRITE
AND
KERNEL
PORT2 [4]
PORT2 [3]
EMUL
INTERRUPT IRQN
ICN COUNTER I/P
BAUDCLK
RESET MRI CLOCK E
8
83BAUD
7-9, 12-16
4
97
84
6
PORT5 [2]
ENABLE RESET I2C
I2C_ADDR
I2C_DATA
I2C_CNTR
I2C_STAT
I2C_CCR
ISCL
I 2 C ISDA
INT
TESTN
CLKBUS IRW ID[7:0]
BAUD RATE
CLOCK
BRG
MRI IRW ID[7:0]
P1 [4]
P1 [3]
I2C_INTERRUPT
IRQTX
IRQWS
IRQBISAT
IRQRX
IRQREQ
IRQN
I2C INTERRUPT
IRQE (EXTERNAL INT.)
IRQPRT0-RESET
IRQPRT1-MASK
IRQPRT2-READ
INTERRUPT
CONTROL
INTERRUPT SOURCE
8·064MHz
IRQSEND
IRQTO
MRI IRW ID[7:0]
INTERRUPTS
PORT4 [4]
PORT3 [3]
PORT3 [7]
PORT4 [2]
IRQRX
IRQBISAT
IRQWS
IRQTX
MODEM
MODPRT0
MODPRT1
MODPRT2
AFC/RXDATA
NOMPLL
MDMSLP
ENMOD
BARPORT
TEST ACCESS ONLY
TXDATA
SAT MANAGEMENT
SELECT
SAT
SAT
GENERATOR
MUX
ID [7:0]
IRW
MRI
C1008
PORT5 [6]
PORT4 [3]
PORT3 [2]
PORT5 P[1]
CLOCK GENERATOR
XOSC-PD
TURBO
CPUCL
ENSIS
CLKENAB
E (CPU CLOCK)
CLKBUS
OUT2 [0]
94
90
99
2
3
1
C1008
LVN1
TO WATCHDOG
AND I2C
63
62
51
89
RESATO
100
61
FILTER
ATO LOGIC
IRQTO
85
CLKBUS IRW TESTN
INP1 [7]
POWDET
PORT3 [4] UPOFFN
P1 [7:0]
DFMS/P2 [4]
DTMS/P2 [3]
IRQN
BAUDCLK
CPUCL/
OUTP2 [0]
C1008
ECLK
XIN
XOUT
TESTN
TXDATA
TXSAT
RXSAT
EXRESN
POFFN
Fig. 3 detailed block diagram of ACE9050
2
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