TQ8017-Q 데이터 시트보기 (PDF) - TriQuint Semiconductor
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TQ8017-Q Datasheet PDF : 8 Pages
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TQ8017
Table 4. DC Characteristics1,2 – Within recommended operating conditions, unless otherwise indicated.
Symbol Parameter
Min
Max
Units
Test Cond.
Notes
VIH
VIL
IIH
IIL
VICM
VIDIF
VIH
VIL
IIH
IIL
VOCM
VODIF
VOH
VOL
IOH
IOL
ICC
PECL Input Voltage High
PECL Input Voltage Low
PECL Input Current High
PECL Input Current Low
PECL Input Common Mode Voltage
PECL Input Differential Voltage (pk-pk)
CMOS/TTL Input Voltage High
CMOS/TTL Input Voltage Low
CMOS/TTL Input Current High
CMOS/TTL Input Current Low
PECL Output Common Mode
PECL Output Differential Voltage
PECL Output Voltage High
PECL Output Voltage Low
PECL Output Current High
PECL Output Current Low
Power Supply Current (+)
VCC –1.1
VTT
–30
VCC – 1.5
400
3.5/2.0
0/0
VCC – 1.5
600
VCC –1.0
VTT
20
0
VCC – 0.5
VCC – 1.5
+30
VCC –1.1
1200
VCC/VCC
1.5/0.8
+200
–100
VCC –1.1
VCC – 0.6
VCC – 1.6
27
8
970
V
V
µA
VIH = VCC – 0.7 V
µA
VIL = VCC – 2.0 V
V
mV
V
2
V
2
µA
VIH = VCC
2
µA
VIL = 0 V
2
V
mV
V
V
mA
mA
mA
Notes: 1. Test conditions unless otherwise indicated: VTT = VCC – 2.0 V, RLOAD = 50 Ω to VTT.
2. Input level is selected by the CNTRL LVL input. Tying CNTRL LVL to GND selects TTL levels, leaving CNTRL LVL OPEN selects
CMOS levels.
Table 5. AC Characteristics1 – Within recommended operating conditions, unless otherwise indicated.
Symbol
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
TR,F
Parameter
Maximum Data Rate/Port
Jitter
Channel Propagation Delay
Ch-to-Ch Propagation Delay Skew
CONFIG to Data Out (Oi) Delay
LOAD Pulse Width
CONFIG Pulse Width
IAi to LOAD High Setup Time
LOAD to IAi Low Hold Time
OAi to LOAD High Setup Time
LOAD to OAi Low Hold Time
Load ↑ to CONFIG ↑
RESET Pulse Width
Output Rise or Fall Time
Min
Typ
Max
Units
Notes
1.25
Gb/s
1,2
150
ps pk-pk
1
2000
ps
3
500
ps
5
ns
7
ns
7
ns
0
ns
3
ns
0
ns
3
ns
0
ns
10
ns
250
400
ps
3
Notes: 1. Test conditions: VCC = 5.0 V; VTT = 3.0 V, RLOAD = 50 Ω to VTT; PECL inputs: VIH = 3.9 V; VIL = 3.5 V; CMOS inputs: VIH = 3.5 V,
VIL = 1.5 V; PECL outputs: VOH > 4.0 V, VOL < 3.4 V; PECL inputs rise and fall times < 1 ns; CMOS inputs rise and fall times
< 20 ns. A bit error rate of 1E–13 BER or better for 223–1PRBS pattern, jitter and rise/fall times are guaranteed through characterization.
2. 1.2 Gb/s Non-Return-Zero (NRZ) data equivalent to 600 MHz clock signal.
3. Rise and fall times are measured at the 20% and 80% points of the transition from VOL max to VOL min.
4
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