SAB9081H 데이터 시트보기 (PDF) - Philips Electronics
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SAB9081H Datasheet PDF : 24 Pages
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Philips Semiconductors
Multistandard Picture-In-Picture (PIP)
controller
Preliminary specification
SAB9081
MAHFP, SAHFP AND SAVFP
Bits MAHfp<3:0>, bits SAHfp<3:0> and byte SAVfp
control the horizontal and vertical inset starting-points of
the acquired data. The horizontal range is 16 steps of eight
28 MHz clock periods when SV2 is set to logic 1. When
SV2 is set to logic 0, the horizontal range is restricted to
eight steps. The vertical range is 256 steps of 1 line/field.
DUVPOL, DVSPOL, DFPOL AND DHSYNC
These bits control the PLL/deflection settings. With
DUVPol, the polarity of the border UV signals can be
inverted when the deflection circuit after the SAB9081
expects inverted signals.
With DVSPol set to logic 0, the SAB9081 triggers on
positive edges of the DVSYNC. If DVSPol is set to logic 1,
it triggers on negative edges. DFPol can invert the field ID
of the incoming fields. Bit DHsync determines the timing of
the DHSYNC pulse. If it is set to logic 0, a burstkey is
expected; if it is set to logic 1, a horizontal sync is expected
at pin DHSYNC.
SUVPOL, SVSPOL, SFPOL AND SHSYNC
These bits control the PLL/decoder settings. With SUVPol,
the polarity of the video UV signals can be inverted when
the decoder circuit before the SAB9081 emits inverted
signals.
With SVSPol set to logic 0, the SAB9081 triggers on
positive edges of the SVSYNC. If it is set to logic 1, it
triggers on the negative edges. SFPol can invert the
field ID of the incoming fields. Bit SHsync determines the
timing of the SHSYNC pulse. If it is set to logic 0, a
burstkey is expected; if it is set to logic 1, a horizontal sync
is expected at pin SHSYNC.
MFIDPON AND SFIDPON
Bits MFidPOn (main field identification position on) and
SFidPOn (subfield identification position on) enable the
field identification position fine tuning. The default value is
off (logic 0), no fine positioning. When on (logic 1), the field
identification position is determined by the value of
bytes MainFidPos and SubFidPos.
BGON
Bit BGOn determines whether the background is visible.
The background has a size of 720 pixels and 240 lines for
NTSC and 720 pixels and 288 lines for PAL. The
background colour can be adjusted with bits BSel, SBBrt
and SBCol.
BON, SBBRT, SBCOL AND BSEL
Bit BOn can switch the sub-borders on (logic 1) or off
(logic 0). Bits SBBrt<1:0> and SBCol<2:0> set the
brightness and colour type of the selected border.
The brightness is set in four levels of 30%, 50%, 70% and
100% IRE. The colour type is one of black (grey), blue, red,
magenta, green, cyan, yellow or white (grey). For black
and white, a finer scale is available.
BSel selects which colour is set, background or border,
see Table 3.
Table 3 BSel modes
BSel<1:0>
00
01
10
11
BORDER COLOUR SET
main
sub
background
sub-border select
MDHFP AND MDVFP
These bytes control the horizontal and vertical positioning
of the main PIP on the screen. The horizontal range is
256 steps of eight 28 MHz clock periods. The vertical
range is 256 steps of 1 line/field.
MHRED
Bits MHRed<5:0>, in a range from 0 to 48, determine the
horizontal reduction factor MHRed/96. If they are set to
logic 0, the PIP is off. If they are set to the maximum value
of 48, the horizontal reduction factor is 0.5.
SHBLOW AND SVBLOW (REPLAY MODE)
Bits SHBlow<5:0> and bit SVBlow are used in the replay
mode. These bits can expand a pixel on the display side
by a factor two (01) or four (11) in the horizontal direction
(SHBlow) and a factor of two (1) in the vertical direction
(SVBlow). Zero values indicate no expansion.
MHBLOW
Bit MHBlow can expand the main picture by a factor of two
in the horizontal direction.
SLSEL (REPLAY MODE)
In the replay PIP mode, bits SLSel<5:0> determine at
which memory location the PIP data is written, the range
depends on the memory usage for each PIP.
The maximum number of PIPs that can be stored in NTSC
mode is 42.
1999 Nov 12
10
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