BS62LV2006 데이터 시트보기 (PDF) - Brilliance Semiconductor
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BS62LV2006 Datasheet PDF : 11 Pages
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n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
VCC
CE2
VCC
tCDR
VIL
Data Retention Mode
VDR≧1.5V
CE2≦0.2V
BS62LV2006
VCC
tR
VIL
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
CL = 5pF+1TTL
CL = 30pF+1TTL
Output
1 TTL
CL(1)
VCC
GND
1. Including jig and scope capacitance.
ALL INPUT PULSES
90%
10%
→←
Rise Time :
1V/ns
90%
10%
→←
Fall Time :
1V/ns
WAVEFORM INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
DESCRIPTION
tAVAX
tRC
Read Cycle Time
tAVQX
tAA
Address Access Time
tE1LQV
tACS1
Chip Select Access Time
tE2HQV
tACS2
Chip Select Access Time
tGLQV
tOE
Output Enable to Output Valid
tE1LQX
tCLZ1
Chip Select to Output Low Z
tE2HQX
tCLZ2
Chip Select to Output Low Z
tGLQX
tOLZ
Output Enable to Output Low Z
tE1HQZ
tCHZ1
Chip Select to Output High Z
tE2LQZ
tCHZ2
Chip Select to Output High Z
tGHQZ
tOHZ
Output Enable to Output High Z
tAVQX
tOH
Data Hold from Address Change
CYCLE TIME : 55ns CYCLE TIME : 70ns
(VCC = 3.0~5.5V)
(VCC = 2.7~5.5V)
MIN. TYP. MAX. MIN. TYP. MAX.
UNITS
55
--
--
70
--
--
ns
--
--
55
--
--
70
ns
(CE1) --
--
55
--
--
70
ns
(CE2) --
--
55
--
--
70
ns
--
--
30
--
--
35
ns
(CE1) 10
--
--
10
--
--
ns
(CE2) 10
--
--
10
--
--
ns
5
--
--
5
--
--
ns
(CE1) --
--
30
--
--
35
ns
(CE2) --
--
30
--
--
35
ns
--
--
25
--
--
30
ns
10
--
--
10
--
--
ns
R0201-BS62LV2006
4
Revision 1.3
May.
2006
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