BR9080 데이터 시트보기 (PDF) - ROHM Semiconductor
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BR9080 Datasheet PDF : 11 Pages
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Memory ICs
BR9080 / BR9080F / BR9080RFV /
BR9016 / BR9016F / BR9016RFV
(3) Read cycle
BR9080 / F / RFV
H
SK
1
4
8
L
H
CS
L
H
DI
L
DO
1 0 1 0 1 0 0 A0 A1
HIGH-Z
H
R/B
WC
High or LOW
16
32
48
tCS
A7 A8
STANDBY
HIGH-Z
D0
D15 D0
D15
tOH
Read Data (n) Read Data (n+1)
Fig.4 BR9080 / F / RFV
BR9016 / F / RFV
H
SK
1
4
8
L
H
CS
L
H
DI
L
DO
1 0 1 0 1 0 A0 A1 A2
HIGH-Z
H
R/B
WC
High or LOW
16
32
48
tCS
A8 A9
STANDBY
HIGH-Z
D0
D15 D0
D15
tOH
Read Data (n) Read Data (n+1)
Fig.5 BR9016 / F / RFV
1) After the fall of the 16th clock pulse, 16-bit data is output from the DO pin in synchronization with the falling edge of the
SK signal.
(DO output changes at a time lag of tPD0, tPD1 because of internal circuit delay following the falling edge of the SK signal.
During the tPD0 and tPD1 timing, the tPD time should be assured before data is read, to avoid the previous data being lost.
See the synchronized data input / output timing chart in Fig.2.)
2)
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