HMS39C7092 데이터 시트보기 (PDF) - Hynix Semiconductor

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HMS39C7092

Embedded Flash MCU

Hynix Semiconductor 

Flash MCU(HMS39C7092)

Introduction

Table 1.1 Pin Descriptions (Continued)

PIN

SYMBOL

DIR

DESCRIPTION

78

P70

AN 0

79

P71

AN 1

80

P72

AN 2

81

P73

AN 3

82

P74

AN 4

83

VSS

O General purpose output of port 7 bit 0

I

ADC Channel 0 input

O General purpose output of port 7 bit 1

I

ADC Channel 1 input

O General purpose output of port 7 bit 2

I

ADC Channel 2 input

O General purpose output of port 7 bit 3

I

ADC Channel 3 input

O General purpose output of port 7 bit 4

I

ADC Channel 4 input

-

Power ground

TIOCA5

I/O PWM output, Compare match output of Reg.A and signal capture input of Timer Ch5

84

nIRQ6

I

External Interrupt Request number 6

P76

I/O General purpose input output of port 7 bit 6

TIOCB5

I/O PWM output, Compare match output of Reg.B and signal capture input of Timer Ch5

85

nIRQ7

I

External Interrupt Request number 7

P77

I/O General purpose input output of port 7 bit 7

86

P75

I/O General purpose input output of port 7 bit 5

87

nIRQ0

P80

I

External Interrupt Request number 0

I/O General purpose input output of port 8 bit 0

nCS3

O External Chip Selection Number 3

88

nIRQ1

I

External Interrupt Request number 1

P81

I/O General purpose input output of port 8 bit 1

nCS2

O External Chip Selection Number 2

89

nIRQ2

I

External Interrupt Request number 2

P82

I/O General purpose input output of port 8 bit 2

nCS1

O External Chip Selection Number 1

90

nIRQ3

I

External Interrupt Request number 3

P83

I/O General purpose input output of port 8 bit 3

91

nC S0

P84

O External Chip Selection Number 0

I/O General purpose input output of port 8 bit 4

92

VSS

-

Power ground

TCLKA

I

External timer input clock A

93

PA0

I/O General purpose input output of port A bit 0

TCLKB

I

External timer input clock B

94

PA1

I/O General purpose input output of port A bit 1

TCLKC

I

External timer input clock C

95

TIOCA0

I/O PWM output, Compare match output of Reg.A and signal capture input of Timer Ch0

PA2

I/O General purpose input output of port A bit 2

TCLKD

I

External timer input clock D

96

TIOCB0

I/O PWM output, Compare match output of Reg.B and signal capture input of Timer Ch0

PA3

I/O General purpose input output of port A bit 3

A23

O External Address Bus bit 23

97

TIOCA1

I/O PWM output, Compare mat ch output of Reg.A and signal capture input of Timer Ch1

PA4

I/O General purpose input output of port A bit 4

Preliminary

19

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