ATF1508AS-15QC160 데이터 시트보기 (PDF) - Atmel Corporation

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ATF1508AS-15QC160

High performance EE PLD

Atmel Corporation 

Features

• High-density, High-performance, Electrically-erasable Complex

Programmable Logic Device

– 128 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 84, 100, 160 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

• Flexible Logic Macrocell

– D/T/Latch Configured Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register within a COM Output

• Advanced Power Management Features

– Automatic 10 µA Standby for “L” Version

– Pin-controlled 1 mA Standby Mode

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages

• Advanced EE Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• Fast In-System Programmability (ISP) via JTAG

• PCI-compliant

• 3.3 or 5.0V I/O Pins

• Security Fuse Feature

• Green (Pb/Halide-free/RoHS Compliant) Package Options

High-

performance

EE PLD

ATF1508AS

ATF1508ASL

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• Transparent-latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• VCC Power-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts

Rev. 0784P–PLD–7/05

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