ATA6621N-PGPW(2007) 데이터 시트보기 (PDF) - Atmel Corporation

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ATA6621N-PGPW
(Rev.:2007)

LIN Transceiver with 5V Regulator and Watchdog

Atmel Corporation 

3. Functional Description

3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),

all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer

nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without

any restrictions.

3.2 Supply Pin (VS)

The LIN operating voltage is VS = 5V to 18V. An undervoltage detection is implemented to dis-

able transmission if VS falls below 5V in order to avoid false bus messages. In this case the

NRES switches to low and the IC enters pre-normal mode. After switching on VS, the IC starts

with the Pre-normal mode and the voltage regulator is switched on (that is, 5V/50 mA output

capability).

The supply current in Sleep mode is typically 10 µA, and 40 µA in Silent mode.

3.3 Ground Pin (GND)

The IC is neutral on the LIN pin in case of GND disconnection; it can handle a ground shift up to

3V for supply voltage at the VS pin above 9V.

3.4 Undervoltage Reset Output (NRES)

This push-pull output is supplied from the VCC voltage. If the VCC voltage falls below the under-

voltage detection threshold of Vthun, NRES switches to low after tres_f (Figure 3-7 on page 13)

except the IC is switched into Sleep mode. Even if VCC = 0V the NRES stays low, because it is

internally driven from the VS voltage. If VS voltage ramps down, NRES stays until VS < 1.5V and

then becomes highly resistant.

The implemented undervoltage delay keeps NRES low for tReset = 10 ms after VCC reaches its

normal value.

3.5 Voltage Regulator Output Pin (VCC)

The internal 5V voltage regulator is capable of driving loads with up to 50 mA of current con-

sumption; it is able to supply the microcontroller and other ICs on the PCB. It is protected

against overloads by means of current limitation and overtemperature shutdown. Furthermore,

the output voltage is monitored and will cause a reset signal at the NRES output pin if the output

voltage drops below a defined threshold Vthun. To boost up the maximum load current, an exter-

nal NPN transistor may be used with its base connected to the VCC pin and its emitter

connected to PVCC.

3.6 Voltage Regulator Sense Pin (PVCC)

This is the sense input pin of the 5V voltage regulator. For normal applications (that is, when

only using the internal output transistor), this pin is connected to the VCC pin. If an external

boosting transistor is used, the PVCC pin must be connected to the output of this transistor, its

emitter terminal.

4 ATA6621N

4887H–AUTO–12/07

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