ATA6621N-PGPW(2007) 데이터 시트보기 (PDF) - Atmel Corporation

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ATA6621N-PGPW
(Rev.:2007)

LIN Transceiver with 5V Regulator and Watchdog

Atmel Corporation 

Figure 3-8.

Power Dissipation: Safe Operating Area versus VCC Output Current and Supply

Voltage VS at Different Ambient Temperatures with Rthja = 35 K/W

55

Tamb = 105˚C

50

45

40

Tamb = 125˚C

35

30

25

20

15

10

5

0

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

VS (V)

For programming purposes at the microcontroller it is potentially necessary to supply the VCC

output via an external supply while the VS pin of the system basis chip is disconnected. This

behavior is no problem for the system basis chip.

3.19 Watchdog

The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge)

or the PTRIG (positive edge) input within a period time window of twd. The trigger signal must

exceed a minimum time ttrigmin > 3 µs. If a triggering signal is not received, a reset signal will be

generated at output NRES. The timing basis of the watchdog is provided by the internal oscilla-

tor, of which the time period Tosc is adjustable via the external resistor Rwd_osc (10 kΩ to 120 kΩ).

In Silent or Sleep mode, the watchdog is switched off to reduce current consumption.

Minimum time for first watchdog pulse is required after the undervoltage reset at NRES disap-

pears and is defined as lead time td.

3.19.1

Typical Timing Sequence with Rwd_osc = 51 kΩ

The trigger signal Twd is adjustable between 2.9 ms and 33 ms via the external resistor Rwd_osc.

For example, with an external resistor of Rwd_oscSC = 51 kΩ ±1%, the typical parameters of the

watchdog come out as follows:

tOSC = 12.5 µs due to 51 kΩ

td = 3922 × 12.5 µs = 49 ms

t1 = 800 × 12.5 µs = 10 ms

t2 = 840 × 12.5 µs = 10.5 ms

tnres = 157 × 12.5 µs = 1.96 ms

After every reset the watchdog always starts with the lead time.

14 ATA6621N

4887H–AUTO–12/07

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