3. Block Diagram
I/O0 - I/O15
AT49BV160D(T)
OUTPUT
BUFFER
INPUT
BUFFER
A0 - A19
INPUT
BUFFER
ADDRESS
LATCH
Y-DECODER
X-DECODER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
Y-GATING
MAIN
MEMORY
COMMAND
REGISTER
WRITE STATE
MACHINE
CE
WE
OE
RESET
WP
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
4. Device Operation
4.1 Command Sequences
When the device is first powered on, it will be in the read mode. In order to perform other device
functions, a series of command sequences are entered into the device. The command
sequences are shown in the “Command Definition Table” on page 15 (I/O8 - I/O15 are don’t care
inputs for the command codes). The command sequences are written by applying a low pulse
on the WE or CE input with CE or WE low (respectively) and OE high. The address and data are
latched by the first rising edge of CE or WE. Standard microprocessor write timings are used.
The address locations used in the command sequences are not affected by entering the com-
mand sequences.
4.2 Read
When the AT49BV160D(T) is in the read mode, with CE and OE low and WE high, the data
stored at the memory location determined by the address pins are asserted on the outputs. The
outputs are put in the high impedance state whenever CE or OE is high. This dual-line control
gives designers flexibility in preventing bus contention.
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