AT34C02C-TH-B(2006) 데이터 시트보기 (PDF) - Atmel Corporation

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AT34C02C-TH-B
(Rev.:2006)

Two-wire Serial EEPROM with Permanent and Reversible Software Write Protect

Atmel Corporation 

AT34C02C [Preliminary]

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is

open-drain driven and may be wire-ORed with any number of other open-drain or open

collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device

address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other

AT24Cxx devices. When the pins are hardwired, as many as eight 2K devices may be

addressed on a single bus system. (Device addressing is discussed in detail under

“Device Addressing,” page 9.) A device is selected when a corresponding hardware and

software match is true. If these pins are left floating, the A2, A1, and A0 pins will be

internally pulled down to GND. However, due to capacitive coupling that may appear

during customer applications, Atmel recommends always connecting the address pins

to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-

mal write operations. When WP is connected directly to Vcc, all write operations to the

memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down

to GND. However, due to capacitive coupling that may appear during customer applica-

tions, Atmel recommends always connecting the WP pins to a known state. When using

a pull-up resistor, Atmel recommends using 10kΩ or less.

Table 2. AT34C02C Write Protection Modes

WP Pin Status

Permanent Write Protect

Register

VCC

GND or Floating

–

Not Programmed

GND or Floating

Programmed

GND or Floating

–

Reversible Write Protect

Register

–

Not Programmed

–

Programmed

Part of the Array Write

Protected

Full Array (2K)

Normal Read/Write

First-Half of Array

(1K: 00H - 7FH)

First-Half of Array

(1K: 00H - 7FH)

Table 3. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 100 kHz, VCC = +1.7V

Symbol Test Condition

Max

CI/O

Input/Output Capacitance (SDA)

8

CIN

Input Capacitance (A0, A1, A2, SCL)

6

Note: 1. This parameter is characterized and is not 100% tested.

Units

pF

pF

Conditions

VI/O = 0V

VIN = 0V

3

5185A–SEEPR–9/06

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