AT25DF641 데이터 시트보기 (PDF) - Atmel Corporation

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AT25DF641

64-Megabit 2.7-volt Minimum SPI Serial Flash Memory

Atmel Corporation 

AT25DF641 [Preliminary]

the device will continue reading back at the beginning of the array (000000h). No delays will be

incurred when wrapping around from the end of the array to the beginning of the array.

Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a

high-impedance state. The CS pin can be deasserted at any time and does not require that a full

byte of data be read.

Figure 7-4. Dual-Output Read Array

CS

SCK

SIO

SO

0 1 2 3 4 5 6 7 8 9 10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

OPCODE

ADDRESS BITS A23-A0

DON'T CARE

OUTPUT

DATA BYTE 1

OUTPUT

DATA BYTE 2

00 111011AAAAAA

MSB

MSB

A A A X X X X X X X X D6 D4 D2 D0 D6 D4 D2 D0 D6 D4

MSB

HIGH-IMPEDANCE

D7 D5 D3 D1 D7 D5 D3 D1 D7 D5

MSB

MSB

MSB

11

3680E–DFLASH–12/08

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