AT24C02A(2004) 데이터 시트보기 (PDF) - Atmel Corporation

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AT24C02A
(Rev.:2004)

Two-wire Serial EEPROM Extended Temperature

Atmel Corporation 

AT24C02A/04A/08A/16A

Device Addressing

The 2K, 4K, and 8K EEPROM devices all require an 8-bit device address word following

a start condition to enable the chip for a read or write operation, as shown in Figure 7.

Figure 7. Device Address

2K

1 0 1 0 A2 A1 A0 R/W

MSB

LSB

4K

1 0 1 0 A2 A1 P0 R/W

8K

1 0 1 0 A2 P1 P0 R/W

16K

1 0 1 0 P2 P1 P0 R/W

Write Operations

The device address word consists of a mandatory “1”, “0” sequence for the first four

most significant bits as shown. This is common to all the EEPROM devices.

The next three bits are the A2, A1, and A0 device address bits for the 2K EEPROM.

These three bits must compare to their corresponding hardwired input pins.

The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a

memory page address bit. The two device address bits must compare to their corre-

sponding hardwired input pins. The A0 pin is no-connect.

The 8K EEPROM only uses the A2 device address bit with the next two bits being for

memory page addressing. The A2 bit must compare to its corresponding hardwired

input pin. The A1 and A0 pins are no-connect.

The 16K EEPROM does not use the device address pins, which limits the number of

devices on a single bus to one. The A0, A1, and A2 pins are no-connects.

The eighth bit of the device address is the read/write operation select bit. A read opera-

tion is initiated if this bit is high, and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is

not made, the chip will return to a standby state.

BYTE WRITE: A write operation requires an 8-bit data word address following the

device address word and acknowledgement. Upon receipt of this address, the EEPROM

will again respond with a “0” and then clock in the first 8-bit data word. Following receipt

of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as

a microcontroller, must terminate the write sequence with a stop condition. At this time,

the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All

inputs are disabled during this write cycle, and the EEPROM will not respond until the

write is complete, as shown in Figure 8.

9

5083A–SEEPR–9/04

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