AS8202 데이터 시트보기 (PDF) - austriamicrosystems AG
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AS8202 Datasheet PDF : 10 Pages
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TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Application Information
Host CPU Interface
The host CPU interface also referred as CNI (communication network interface) connects the
application circuitry to the TTP controller. All ram_-lines provide asynchronous read/write
access to a dual ported RAM. There are no setup/hold constraints referred to the microtick
(main clock “clk0”). The signals have to be applied for certain duration to be synchronized to
the main internal clock (microtick). The time_-lines signal to host CPU the global synchronous
time of the TTP network and determine when to deliver, resp. to fetch data from the host
interface. One of the lines may be connected to an interrupt input of the host CPU. Note that
the microtick, time_overflow and the time_tick pins can be configured as general purpose
output LED pins (see the LED Interface section below).
Host Interface Ports
Pin Name
ram_address[0:11]
ram_data[0:15]
ram_ceb
ram_web
ram_oeb
ram_readyb
time_overflow
microtick
time_signal
time_tick
mode
in
inout (tri)
In
In
In
out
out
out
out
out
width
12
16
1
1
1
1
1
1
1
1
comment
DPRAM address bus, 12 bit
DPRAM data bus, 16 bit
DPRAM chip enable
DPRAM write enable
DPRAM output enable
DPRAM ready
Overflow of global time (global time is Zero)
Microtick (internal main clock)
CNI time signal
Macrotick (global time is incremented)
Asynchronous DPRAM interface
Signals ram_address[0:11] and ram_web have to be stable before the falling edge of ram_ceb
For a write access the host sets ceb, web, address and data until the DPRAM has taken the
data and set readyb active low. The next access may start with readyb inactive again. A read
cycle starts with valid address and ceb, the data is valid with readyb active low. A low level on
oeb and ceb switches the data bus from tristate to output. Access times depend on the
controller clock rate and controller activity, typical values are:
controller cycle time
write time
read time
readyb low time
Tc
Min 25 ns (40 MHz)
Tw
Min 4 Tc
Tr
Min 5 Tc
Trb
Min 1 Tc
ceb
addres
data
web
oeb
ready
b
write
valid
valid
Tw
tristate
read
valid
xx
valid
Trb
Tr
Trb
Rev. 1.0, October 2000
Page 7 of 7
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