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AS6C6264
8K X 8 BIT LOW POWER CMOS SRAM
Alliance Semiconductor
AS6C6264 Datasheet PDF : 12 Pages
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®
8K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
t
RC
*
= Read Cycle Time
SYMBOL
TEST CONDITION
V
DR
CE#
≧
V
CC
- 0.2V
or CE2
≦
0.2V
V
CC
= 1.5V
I
DR
CE#
≧
V
CC
- 0.2V
or CE2
≦
0.2V
t
CDR
See Data Retention
Waveforms (below)
t
R
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE#
controlled)
Vcc
CE#
Vcc(min.)
t
CDR
V
IH
V
DR
≧
1.5V
CE#
≧
Vcc-0.2V
MIN.
1.5
-
0
t
RC
*
TYP.
-
0.5
-
-
MAX.
5.5
UNIT
V
10
µA
-
ns
-
ns
Vcc(min.)
t
R
V
IH
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
Vcc
CE2
Vcc(min.)
t
CDR
V
IL
V
DR
≧
1.5V
CE2
≦
0.2V
Vcc(min.)
t
R
V
IL
Page 7 of 12
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