AS6C2008-55TIN 데이터 시트보기 (PDF) - Alliance Semiconductor

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AS6C2008-55TIN

256K X 8 BIT LOW POWER CMOS SRAM

Alliance Semiconductor 

February 2007

Rev. 1.1

AS6C2008

®

256K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS

PARAMETER

SYMBOL TEST CONDITION

VCC for Data Retention

VDR

CE# ≧ VCC - 0.2V

or CE2 ≦ 0.2V

Data Retention Current

VCC = 1.5V

-

I IDR CE# ≧ VCC - 0.2V -

or CE2 ≦ 0.2V -I*

Chip Disable to Data

Retention Time

tCDR

See Data Retention

Waveforms (below)

Recovery Time

tR

tRC* = Read Cycle Time **I= Industrial temperature

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (CE# controlled)

Vcc

CE#

Vcc(min.)

tCDR

VIH

VDR ≧ 1.5V

CE# ≧ Vcc-0.2V

MIN.

1.5

TYP.

-

MAX.

3.6

UNIT

V

-

0.5

10

µA

0

-

-

ns

tRC*

-

-

ns

Vcc(min.)

tR

VIH

Low Vcc Data Retention Waveform (2) (CE2 controlled)

Vcc

CE2

Vcc(min.)

tCDR

VIL

VDR ≧ 1.5V

CE2 ≦ 0.2V

Vcc(min.)

tR

VIL

10/February/07, v.1.0

Alliance Memory Inc.

Page 7 of 13

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