STK11C48(2002) 데이터 시트보기 (PDF) - Simtek Corporation
부품명
상세내역
일치하는 목록
STK11C48 Datasheet PDF : 10 Pages
| |||
STK11C48
SRAM READ CYCLES #1 & #2
NO.
1
2
3
4
5
6
7
8
9
10
11
SYMBOLS
#1, #2
Alt.
tELQV
tAVAVf
tAVQVg
tGLQV
tAXQXg
tELQX
tEHQZh
tGLQX
tGHQZh
tELICCHe
tEHICCLd, e
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
(VCC = 5.0V + 10%)
STK11C48-25 STK11C48-35 STK11C48-45
UNITS
MIN MAX MIN MAX MIN MAX
25
35
45
ns
25
35
45
ns
25
35
45
ns
10
15
20
ns
5
5
5
ns
5
5
5
ns
10
13
15
ns
0
0
0
ns
10
13
15
ns
0
0
0
ns
25
35
45
ns
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
SRAM READ CYCLE #2: E Controlledf
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
11
tEHICCL
7
tEHQZ
G
DQ (DATA OUT)
ICC
4
8
tGLQV
tGLQX
10
tELICCH
STANDBY
ACTIVE
9
tGHQZ
DATA VALID
December 2002
3 Document Control # ML0003 rev 0.0
Share Link: 