APL3225 데이터 시트보기 (PDF) - Anpec Electronics
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APL3225 Datasheet PDF : 15 Pages
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APL3225
Function Description
ACIN Power-On-Reset (POR)
The APL3225 is built-in a power-on-reset circuit to keep
the output shut off until internal circuitry is operating
properly. The POR circuit has hysteresis and a de-glitch
feature so that it will typically ignore undershoot transients
on the input. When input voltage exceeds the POR thresh-
old and after 8ms blanking time, the output voltage starts
a soft-start to reduce the inrush current.
ACIN Over-Voltage Protection (OVP) and LDO Mode
Operation
The CHR_LDO output of the IC operates similar to a lin-
ear regulator. When the ACIN input voltage is less than
VREG, and above the ACIN POR VACIN, the internal LDO
output voltage tracks the input voltage with a voltage drop
caused by RDS(on) of MOSFET Q1. When the ACIN input
voltage is greater than V plus the R drop of Q1,
REG
DS(on)
and less than V , the internal LDO output voltage is
OVP
regulated to VREG, and this is also referred as LDO mode
operation. If the input voltage rises above VOVP, the inter-
nal FET Q1 and Q2 will be turned off within 1µs to protect
connected system on OUT pin. When the input voltage
returns below the input OVP threshold minus the
hysteresis, the FETs is turned on again after 1ms recov-
ery time. The input OVP circuit has a 200mV hysteresis
and a recovery time of TON(OVP) to provide noise immunity
against transient conditions.
Charging Current Control
The charging current is controlled by the GATDRV pin.
When sourcing a current from the GATDRV pin, the OUT
pin delivers the charging current which is 200-fold mag-
nified in amplitude based on GATDRV’s current. The I
OUT
current can be calculated by this following equation:
Current Limit
The output current is monitored by the internal current
limit circuit. When the output current reaches the current
limit threshold, the device limits the output current at cur-
rent limit threshold. The current limit level decrease as
the junction temperature increase. When the Junction
temperature increases, the internal current limit circuit
reduces the current limit level, allowing the device’s Junc-
tion temperature to cool down.
Internal P-MOSFET and Reverse Current Blocking
The APL3225 integrates a P-channel MOSFET with the
body diode reverse protection to replace the external PNP
transistor and Schottky diode for cell phone’s PMIC. The
body diode reverse protection prevents battery voltage
supplies to CHR_LDO and ACIN pin. When the P-chan-
nel MOSFET’s negative VSD voltage is detected, the inter-
nal bulk selection circuitry will switch the body diode of
the P-channel MOSFET forward biased from source to
drain, meanwhile the P-channel is turned off regardless
of GATDRV’s current. This after the detection of negative
V , the P-channel MOSFET is in lockout state to prevent
SD
battery discharging from ACIN and CHR_LDO to external
circuitry. The P-channel MOSFET lockout will be releases
when positive VSD is detected.
OUT Overshoot Clamp
This OUT pin possesses the overshoot clamp function to
limit peak voltage. Since the clamping function needs a
low resistance path between OUT pin and external high
voltage source (in abnormal condition), please connect
this OUT pin directly to outside circuit to let clamping work.
IOUT=200xIGATDRV
where
The I is the current flowing out from OUT pin.
OUT
The IGATDRV is the current flowing out from GATDRV pin.
Copyright © ANPEC Electronics Corp.
7
Rev. A.1 - Nov., 2012
www.anpec.com.tw
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