AN666 데이터 시트보기 (PDF) - Silicon Laboratories
부품명
상세내역
일치하는 목록
AN666 Datasheet PDF : 34 Pages
| |||
AN666
4. DMA Overview
The DMA consists of two modules: DMA controller (DMACTRL) and DMA peripheral crossbar (DMAXBAR). The
controller provides a single access point for all 16 (SiM3U1xx and SiM3C1xx) or 10 (SiM3L1xx) DMA channels and
the global DMA controls. The controller is also responsible for handling arbitration between channels. The DMA
peripheral crossbar assigns channels to a peripheral. When assigned and properly configured, the peripheral’s
data request signal will trigger a DMA channel to transfer data. Figure 2 shows a block diagram of the DMA
controller and DMA peripheral crossbar.
DMACTRLn
Module
Channel Control
Channel Status
Channel Software
Transfer Request
Global Controller
State and Enable
Arbitration
SiM3xxxx
RAM
DMA Channel 0
(DMAn_CH0)
DMA Channel 1
(DMAn_CH1)
Source Pointer
Destination Pointer
Configuration
Source Pointer
Destination Pointer
Configuration
DMA Channel n
(DMAn_CHx)
Source Pointer
Destination Pointer
Configuration
DMAXBARn
Module
Peripheral 0.0
Peripheral 0.1
Peripheral 0.2
Peripheral 0.3
Peripheral 0.x
Peripheral 1.0
Peripheral 1.1
Peripheral 1.2
Peripheral 1.3
Peripheral 1.y
Peripheral n.0
Peripheral n.1
Peripheral n.2
Peripheral n.3
Peripheral n.z
Figure 2. DMACTRL and DMACH Block Diagram
The channels have controls and flags in the DMACTRL registers. In addition, each channel has one or more
transfer descriptors stored in memory that describe the data transfer in detail. Each channel can have primary,
alternate, or scatter-gather descriptors. The BASEPTR and ABASEPTR registers in the controller point to the
starting address of these descriptors in memory. Firmware sets the BASEPTR field, and the controller hardware
automatically sets the ABASEPTR field based on the number of channels implemented in the module.
Each channel has separate enables, alternate enables, masks, software requests, programmable priority, and
status flags. The channels operate independently, but have a fixed arbitration order.
The STATE field reports the current status of the DMA controller, and the DMAENS bit indicates whether the global
DMA enable is set.
2
Rev. 0.1
Share Link: 