AN-9046 데이터 시트보기 (PDF) - Fairchild Semiconductor

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AN-9046

Assembly Guidelines for Dual Power56 Packaging

Fairchild Semiconductor 

[2] Bryant, Keith, “Investigating Voids,”

Circuits Assembly, June 2004

[3] Comley, David, et al, “The QFN: Smaller,

Faster and Less Expensive,” Chip Scale

Review.com, August/September 2002

[4] Englemaier, Werner, “Voids in solder

joints-reliability,” Global SMT & Package,

December 2005

[5] IPC Solder Products Value Council,

“Round Robin Testing and Analysis of

Lead Free Solder Pastes with Alloys of Tin,

Silver and Copper,” 2005

[6] IPC-A-610-D, “Acceptance of Electronic

Assemblies,” February 2005

[7] IPC J-STD-001D, “Requirements for

Soldered Electrical and Electronic

Assemblies,”

[8] IPC-SM-7525A, “Stencil Design

Guidelines,” May 2000

[9] JEDEC, JESD22-B102D, “Solderability,”

VA, Sept. 2004

[10]

Syed, Ahmer, et al, “Board Level

Assembly and Reliability Considerations

for QFN Type Packages,” Amkor

Technology, Inc., Chandler, AZ

Applicable FSIDs: FDMS9600S, FDMS9620S

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