AN-9037 데이터 시트보기 (PDF) - Fairchild Semiconductor
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AN-9037 Datasheet PDF : 7 Pages
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have already been taken into consideration on the
recommended footprint given on the datasheet. It
is recommended the customer follow this
footprint to assure best assembly and ultimately
reliability performance, as well as from a thermal
performance.
PAD FINISH
The most frequently encountered pad finish for
consumer electronics with tin lead solders was hot
air solder leveled, HASL. With lead free, other
finishes are preferred. Immersion silver,
immersion nickel gold and organic surface
protectant, OSP is the board finishes of choice.
Each finish has useful properties, and each has its
challenges. It is beyond the scope of this paper to
debate each system’s merits. Not any one finish
will be right for all applications, but currently the
most commonly seen in large scale consumer
electronics is OSP. A high quality OSP like
Enthone® Entek® Plus HT is recommended.
PWB MATERIAL
It is recommended that lead free FR-4 is used in
PWB construction. Lower quality FR-4 can cause
numerous problems with the reflow temperatures
seen when using lead free solder. IPC-4101B
“Specification for Base Materials for Rigid and
Multilayer Printed Boards” contains further
information on choosing the correct PWB material
for the intended application.
USING VIAS WITH 8X8 MLP
Often the designer will wish to place vias inside of
the three thermal pads. While this is acceptable,
the user should realize that vias often create
voiding, and should carefully study the process
design with x-ray inspection of voiding to assure
the design is yielding the expected performance.
There are several types of via. Blind vias are not
recommended due to the fact they often trap gases
generated during reflow and yield high percentages
of voiding. Solder mask can also be placed over
the top of the via to prevent solder from wicking
down the via. It has been shown in previous
studies that this will also create a higher incidence
of voiding than an open through-hole or filled via.
If through hole vias are used, a drill size of 0.3mm
with 1 ounce copper plating yields good
performance. With through-hole vias, solder
wicking through the hole, or solder protrusion,
must be considered. In high reliability applications,
filled vias are the preferred due to lower incidences
of voiding during reflow and eliminating the stress
riser created by a void at the edges of the via barrel.
Figure 3: PWB pad showing OSP pad finish
and vias.
STENCIL DESIGN
It is estimated that 60% of all assembly errors are
due to paste printing. For a robust manufacturing
process, it is therefore the most critical phase of
assembly. Due to the importance of the stencil
design, many stencil types were tried to determine
the optimal stencil design for the recommended
footprint pad, on a typical application board with
Organic Surface Protectant (OSP) surface finish,
thermal vias, on FR-4. Solder paste coverage for
the thermal pads was printed ranging from 50-65%
coverage. To allow gases to escape during reflow
it is recommended that the paste be deposited in a
grid allowing “channels” for gases to vent. It was
found that 52% coverage yielded good void
performance, while maintaining good standoff
height. The paste was printed from a 5 mil thick
stainless steel stencil. Various other stencil
apertures can be used, such as circles, but were not
studied here. The paste is printed on the outer
pins with a slightly reduced ratio to the PWB pad.
Per IPC-7525 “Stencil Design Guidelines” gives a
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