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AM79C983ASKC

Integrated Multiport Repeater 2 (IMR2™)

Advanced Micro Devices 

PRELIMINARY

SQE Test Status ...................................................................................................... 39

Register Bank 5: RMON Registers .................................................................................. 39

etherStatsOctets ...................................................................................................... 39

etherStatsPkts.......................................................................................................... 39

etherStatsBroadcastPkts.......................................................................................... 40

etherStatsMulticastPkts............................................................................................. 40

etherStatsCRCAlignErrors ........................................................................................ 40

etherStatsUndersizePkts.......................................................................................... 40

etherStatsOversizePkts............................................................................................ 40

etherStatsFragments................................................................................................ 40

etherStatsJabbers .................................................................................................... 40

etherStatsCollisions ................................................................................................. 40

etherStats64Octets .................................................................................................. 40

etherStats65to127Octets ......................................................................................... 40

etherStats128to255Octets ....................................................................................... 40

etherStats256to511Octets ....................................................................................... 40

etherStats512to1023Octets ..................................................................................... 40

etherStats1024to1518Octets ................................................................................... 40

Activity...................................................................................................................... 40

Register Bank 7: Management Support........................................................................... 40

Device ID.................................................................................................................. 40

Sample Error Status................................................................................................. 40

Report Packet Size .................................................................................................. 41

STATS Control ......................................................................................................... 41

Register Banks 16 through 30: Port Attribute Registers .................................................. 41

Readable Frames..................................................................................................... 42

Readable Octets ...................................................................................................... 42

Frame Check Sequence (FCS) Errors ..................................................................... 42

Alignment Errors ...................................................................................................... 42

Frames Too Long..................................................................................................... 42

Short Events............................................................................................................. 43

Runts........................................................................................................................ 43

Collisions.................................................................................................................. 43

Late Events .............................................................................................................. 43

Very Long Events..................................................................................................... 43

Data Rate Mismatches............................................................................................. 43

Auto Partitions.......................................................................................................... 44

Source Address Changes ........................................................................................ 44

Readable Broadcast Frames ................................................................................... 44

Last Source Address................................................................................................ 44

Readable Multicast Frames ..................................................................................... 44

Preferred Source Address........................................................................................ 44

SYSTEM APPLICATIONS .................................................................................................................. 45

IMR2 to QuIET Connection........................................................................................................... 45

Other Media .................................................................................................................................. 45

MAC Interface ............................................................................................................................... 45

RAUI Port ............................................................................................................................... 45

PR Port Configuration ............................................................................................................ 45

Port Switching ............................................................................................................................... 48

ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 50

OPERATING RANGES................................................................................................................. 50

DC CHARACTERISTICS over operating ranges unless otherwise specified............................... 50

SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified ............... 51

KEY TO SWITCHING WAVEFORMS................................................................................................ 54

SWITCHING WAVEFORMS .............................................................................................................. 54

Master Clock (MCLK) Timing........................................................................................................ 54

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Am79C983A

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