P3055LD 데이터 시트보기 (PDF) - Niko Semiconductor

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P3055LD

25V; 12A N-channel logic level enhancement mode field effect transistor

Niko Semiconductor 

NIKO-SEM

N-Channel Logic Level Enhancement

Mode Field Effect Transistor

P3055LDG

TO-252 (DPAK)

Lead-Free

On-State Drain Current1

Drain-Source On-State

Resistance1

Forward Transconductance1

ID(ON)

RDS(ON)

gfs

VDS = 10V, VGS = 10V

VGS = 5V, ID = 12A

VGS = 10V, ID = 12A

VDS = 15V, ID = 12A

12

A

70 120

mΩ

50 90

16

S

DYNAMIC

Input Capacitance

Ciss

450

Output Capacitance

Coss

VGS = 0V, VDS = 15V, f = 1MHz

200

pF

Reverse Transfer Capacitance

Crss

60

Total Gate Charge2

Qg

15

Gate-Source Charge2

Qgs

VDS = 0.5V(BR)DSS, VGS = 10V,

2.0

nC

Gate-Drain Charge2

Qgd

ID = 6A

7.0

Turn-On Delay Time2

td(on)

6.0

Rise Time2

Turn-Off Delay Time2

tr

VDS = 15V, RL = 1Ω

6.0

nS

td(off)

ID ≅ 12A, VGS = 10V, RGS = 2.5Ω

20

Fall Time2

tf

5.0

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)

Continuous Current

Pulsed Current3

Forward Voltage1

IS

ISM

VSD

IF = IS, VGS = 0V

12

A

20

1.5 V

Reverse Recovery Time

trr

30

nS

Peak Reverse Recovery Current

IRM(REC)

IF = IS, dlF/dt = 100A / µS

15

A

Reverse Recovery Charge

Qrr

1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%.

2Independent of operating temperature.

3Pulse width limited by maximum junction temperature.

0.043

µC

REMARK: THE PRODUCT MARKED WITH “P3055LDG”, DATE CODE or LOT #

Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.

2

AUG-17-2004

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