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PM15CZF120_

USING INTELLIGENT POWER MODULES

MITSUBISHI ELECTRIC  

MITSUBISHI SEMICONDUCTORS POWER MODULES MOS

USING INTELLIGENT POWER MODULES

temperature protection circuit.

The over temperature function pro-

vides effective protection against

overloads and cooling system fail-

ures in most applications. However,

it does not guarantee that the maxi-

mum junction temperature rating of

the IGBT chip will never be ex-

ceeded. In cases of abnormally

high losses such as failure of the

system controller to properly regu-

late current or excessively high

switching frequency it is possible

for IGBT chip to exceed Tj(max) be-

fore the base plate reaches the OT

trip level.

Caution:

Tripping of the over-temperature

protection is an indication of stress-

ful operation. Repetitive tripping

should be avoided.

6.4.4 Over-Current Protection

rent is detected a controlled shut-

down is initiated and a fault output

is generated. The controlled shut-

down lowers the turn-off di/dt which

helps to control transient voltages

that can occur during

shut down from high fault currents.

Most Intelligent Modules use the

two step shutdown depicted in Fig-

ure 6.17. In the two step shutdown,

the gate voltage is reduced to an

intermediate voltage causing the

current through the device to drop

slowly to a low level. Then, about

5µs later, the gate voltage is re-

duced to zero completing the shut

down. Some of the large six and

seven pack IPMs use an active

ramp of gate voltage to achieve the

desired reduction in turn off di/dt

under high fault currents. The oscil-

lographs in Figure 6.18 illustrate

Figure 6.15 Operation of Under-Voltage Lockout

INPUT

SIGNAL

UVr

UVt

CONTROL

SUPPLY

VOLTAGE

FAULT

OUTPUT

CURRENT

(IFO)

tFO

tdUV

tFO

tdUV

The IPM uses current sense IGBT

chips to continuously monitor

power device current. If the current

though the Intelligent Power Mod-

ule exceeds the specified

overcurrent trip level (OC) for a pe-

riod longer than toff(OC) the IPMs

internal control circuit will protect

the power device by disabling the

gate drive and generating a fault

output signal. The timing of the

over-current protection is shown in

Figure 6.17. The toff(OC) delay is

implemented in order to avoid trip-

ping of the OC protection on short

pulses of current above the OC

level that are not dangerous for the

power device. When an over-cur-

INTERNAL

GATE

VOLTAGE

VGE

CONTROL SUPPLY ON

SHORT

GLITCH

IGNORED

POWER SUPPLY

FAULT AND

RECOVERY

Figure 6.16 Operation of Over-Temperature

INPUT

SIGNAL

OT

OTr

BASE PLATE

TEMPERATURE

(Tb)

CONTROL SUPPLY OFF

FAULT OUTPUT

CURRENT

(IFO)

INTERNAL

GATE

VOLTAGE

VGE

Sep.1998

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