AK5356VN 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AK5356VN

Low Power 20-Bit ADC with MIC-Amp & PGA

Asahi Kasei Microdevices 

ASAHI KASEI

[AK5356]

n System Reset

The AK5356 is placed in the power-down mode by bringing PDN pin “L”. The control registers are also reset at the same

time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down

mode. The output data SDTO becomes available after 4128 cycles of LRCK clocks. During initialization, the ADC digital

data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle to the data corresponding to the

input signal at the end of initialization (Settling time equals the group delay time approximately.).

As a normal initialization cycle may not be executed, nothing writes at address 01H during

initialization cycle after exiting power-down by PDN pin.

Power Supply

PDN pin

PDN pin may be “L” at power-up.

ADC Internal

State

PD

4128/fs

INIT -1

GD

AIN

SDTO

“0”data

Control register

INIT -2

Normal

PM

GD (1)

4128/fs

INIT -1

Normal

GD

(2)

(3) “0”data

(1)

Idle Noise

Normal

W rite to register

Inhibit

Normal

External clocks

(4)

The clocks may be stopped.

(5)

Figure 10. Power-Up / Power-Down Timing Example

• PD:

• PM:

• INIT-1:

• INIT-2:

• Inhibit:

Power-down state. ADC is output “0”.

Power-down state by Power Management bit. ADC is output “0”.

Initialization cycle of ADC

Initializing all control registers.

Inhibits writing to all control registers.

Note: See “Register Definitions” about the condition of each register.

(1). Digital output corresponding to the analog input is delayed by the Group Delay amount (GD). Output signal

gradually comes to settle to input signal during a group delay.

(2). If the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of

a internal.

(3). ADC output data is “0” at power-down.

(4). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5356 should be placed in the

power-down state.

(5). When external clocks are not supplied, inhibits writing to all control registes.

MS0171-E-00

- 15 -

2002/08

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