AK8443 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
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AK8443 Datasheet PDF : 29 Pages
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[AK8443]
Clock Input pin SDCLK and Data Input pin SDATA for Serial Interface are shared with A/D Data
Output pins, D0 and D1 respectively. When SDENB becomes low, D0 and D1 are put into High-Z
conditions and it is enabled to input SDCLK and SDATA. SDATA is captured at the rising edge of
SDCLK. SDATA is 16 Bit long. Write “zeros“ from first Bit to 4th Bit. 5th ~8th Bits are assigned for
Register Address where the 5th Bit is MSB and the 8th Bit is LSB. 9th~ 16th Bits are assigned for
Data where the 9th Bit is MSB and the 16th Bit is LSB.
16 and more rising edges of SDCLK are required while SDENB is low, from the time to fall to the
time to rise. When it is less than 16 rises, registers will not be written properly.
If it is more than 16 rises while SDENB is low, from falling to rising, the last 16 edges become
effective. There is a possibility that an erroneous data will be written into registers if noises occur
on D0 Output / SDCLK input pin and D1 Output / SDATA input pin when these pins are at High-Z
conditions. To avoid this, resistors should be connected between D0 / SDCLK pin, D1 / SDATA
pin and AVSS respectively to pull-down these pins.
SDENB
D0
SDCLK
D1
SDATA
High-Z
High-Z
0 0 0 0 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
Wright Register
00
MS1280-E-00
17
2011/8
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