AKM8411VT 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AKM8411VT

Single Channel Input, 16 Bit 5 MSPS Video ADC

Asahi Kasei Microdevices 

ASAHI KASEI

[AK8411]

„ Input Circuit

DC Direct Coupled Mode

A mode to capture a difference between the sampled signal level at the Sample & Hold

circuit and the reference level to be input on VCLP. It is effective when the Pixel signal level

is output at higher than the reference level.

MCLK

TSMP

Timing

Control

VCLP

0.1uF

CIS

CISIN

SHD H: Sample

L: Hold

Sample &

Hold

Offset

DAC

Fig. 3 in DC Direct Coupled Mode

CDS Mode

A mode to sample feed-through level of CIS signal (CCD type) and data level, and its

difference is captured. In this scheme, thermal noise overlapped with CIS signal and shift of

Clamp level is cancelled out. It is effective when the pixel signal level is output at lower than

the reference level.

MCLK

TSMP

VCLP

Timing

Control

CIS

VCLP

Clamp

Switch

CISIN

SHR

H: Close

L: Open

Clamp

Circuit

SHR

H: Sample

L: Hold

Sample &

Hold #1

Sample &

Hold #2

SHD H: Sample

L: Hold

Offset

DAC

Fig. 4 in CDS Mode

MS0457-E-00

5

2006/05

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