AK7712 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AK7712

Built-in 20-bit ADC/DAC Sophisticated Audio DSP

Asahi Kasei Microdevices 

ASAHI KASEI

[AK7712A-VT]

„ AK7712A Control Signal, Input/Output Data Signal, Reset, etc.

Pin No Pin name I/O

Function

6

RST

I Reset input ("L" Reset)

(note 1)

5

PD

I Power down

(note 1)

3

PDAD

I AD reset control

(note 1)

4

PDDA

I DA reset control

(note 1)

19 SDIN1

I Serial data input 1

MSB justified 16-•24-bit / LSB justified 16-•24-bit

18 SDOUT1 O Serial data output 1

MSB justified 16-•24-bit / LSB justified 16-bit

12 SDIN2

I Serial data input 2 (OPCL : "H" )

(note 2)

MSB justified 16-•20-bi

13 SDAD

O Serial data output 2 (OPCL : "H" )

(note 3)

MSB justified 16-•20-bit, common set-up with SDIN2

15 SDDA

I Serial data input 3 (OPCL : "H" )

(note 2)

MSB justified 16-•20-bit, common set-up with SDOUT2

14 SDOUT2 O Serial data output 3 (OPCL : "H" )

(note 3)

MSB justified 16-•20-bit

16 SDDA2

I Serial data input 4 (OPCL : "H" )

(note 2)

MSB justified 20-bit (16-bit at BCLK=32fs )

17 SDOUT3 O Serial data output 4 (OPCL : "H")

(note 3)

MSB justified 20-bit (16-bit at BCLK=32fs)

21 BCLK

I/O Clock input/output for serial data input

22 LRCK

I/O L/R channel identify signal input/output

Interface clock select

20 SMODE

I Input/output set-up for each clock pin of LRCK and BCLK

"L":slave mode(21,22 input), "H":master mode(output)

23 CLKO

O Master clock output

(note 4)

27 XTO

O Output for quartz oscillator

When an external clock is input, this pin should be left floating.

26 XTI

I Input for quartz oscillator

A crystal can be connected between this pin and XTO, or an external CMOS

clock can be input on this pin.

note:1 About the directions, please refer the paragraph of power down reset control on P.65.

2 Set to "L" or "open" when OPCL is "L".

3 The output is "L" when OPCL is "L".

4 During a timing of changing CONTROL REGISTER, CLKO is instability.

0180-E-02

-9-

1997/12

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