AK5384 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
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AK5384 Datasheet PDF : 21 Pages
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ASAHI KASEI
[AK5384]
Parameter
Symbol
min
Audio Interface Timing (Slave mode)
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Period
tBCK
160
BICK Pulse Width Low
tBCKL
65
Pulse Width High
tBCKH
65
LRCK Edge to BICK “↑”
(Note 11) tLRB
30
BICK “↑” to LRCK Edge
(Note 11) tBLR
30
LRCK to SDTO1/2 (MSB) (Except I2S mode) tLRS
BICK “↓” to SDTO1/2
tBSD
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO1/2
tBCKH
32
(Note 11) tLRB
20
(Note 11) tBLR
20
tBSD
TDM128 mode (TDM1=“H”, TDM0=“H”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO1
tBCKH
32
(Note 11) tLRB
20
(Note 11) tBLR
20
(Note 12) tBSD
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Frequency
fBCK
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1/2
dBCK
tMBLR
−20
tBSD
−40
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Frequency
fBCK
BICK Duty
(Note 13) dBCK
BICK “↓” to LRCK
BICK “↓” to SDTO1/2
tMBLR
−12
tBSD
−20
TDM128 mode (TDM1=“H”, TDM0=“H”)
BICK Frequency
fBCK
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1
dBCK
tMBLR
−12
(Note 12) tBSD
−20
Power-Down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO1/2 valid
(Note 14) tPD
150
(Note 15) tPDV
typ
max
35
35
20
20
64fs
50
20
40
256fs
50
12
20
128fs
50
12
20
516
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. SDTO2 output is fixed to “L”.
Note 13. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 14. The AK5384 can be reset by bringing the PDN pin = “L”.
Note 15. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
MS0225-E-00
-8-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
Hz
%
ns
ns
Hz
%
ns
ns
ns
1/fs
2003/05
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