AK5371 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AK5371

2ch A/D Converter with USB I/F

Asahi Kasei Microdevices 

ASAHI KASEI

[AK5371]

Digital DC Characteristics

Ta=0 - 70°C; VD=3.0 - 3.6V; DGND=0V Measurement under static state

All digital pins except DP, DN. Schmitt hysteresis level of RST pin and levels of all test pins will not be tested.

Parameter

Symbol

Min

Typ

Max

EPDI, EPEN, EPSEL, pin “H” level input voltage

VIH

70%VD

EPDI, EPEN, EPSEL pin “L” level input voltage

VIL

30%VD

RSTN pin “H” level voltage

VIHR

2.0

RSTN pin “L” level voltage

VILR

0.8

CS, SK, EPAO, SUSN pin “H” level output

VOH

2.4

voltage IOH = 2mA

CS, SK, EPAO, SUSN pin “L” level output

VOL

0.6

voltage

IOL = -2mA

Input Leakage Current

Iin

±10

Units

V

V

V

V

V

V

µA

Switching Characteristics

Ta=25°C, VA=VD=3.3V

Parameter

Symbol

Min

Typ

Max

Master Clock Frequency

MCLK

-

11.2896

-

Reset input width @RSTN pin(low active)

Wrst

1.0

DP,DN Single Ended Receiver Threshold

for H level

VseH

2.0

for L level

VseL

0.8

Time Width for USB Reset Signal Recognition*1

DP<VseL & DN< VseL to USB Reset mode

Trst_rec

2.7

Device Ready Time from USB Reset

Ready for transaction after reset

Tdrr

10

Time Width for Suspend Recognition

Idle state ( DP > VseL & DN < VseL )

Tsus_rec

3.0

to Suspend mode

Resume Time from Suspend

First flip of DP/DN from Idle sate

Tresm

30

To Device Ready*)

Device Ready: VREF, X’tal oscillator, and PLL get stable and bus transaction with normal rate is ready.

Units

MHz

us

V

µs

ms

ms

ms

min 20ms

resume time

min 10ms

resume recovery time

VD

DP

DN

RSTN

PLL

Clock

Device

Connected

Resume

Tdrr

Reset Mode

Trst_rec

Figure 1. Mode change with respect to BUS States 1 (Power on and device connected)

MS0103-E-00

MS0103-E-00

7

2001/06

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