MWS5101ELS 데이터 시트보기 (PDF) - Intersil

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MWS5101ELS

256-Word x 4-Bit LSI Static RAM

Intersil 

MWS5101, MWS5101A

A0 - A7

CHIP SELECT 1

CHIP SELECT 2

OUTPUT DISABLE

READ/WRITE

DATA OUT

tRC

tDOA1

tDOA2

tDOA3

tDOH1

tDOH2

tDOH3

tAA

HIGH

IMPEDANCE

DATA OUT

VALID

FIGURE 1. READ CYCLE TIMING WAVEFORMS

HIGH

IMPEDANCE

A0-A7

CHIP SELECT 1

tCS1S

tWC

tWR

tCS1H

CHIP SELECT 2

OUTPUT DISABLE

DI1-DI4

tCS2S

tCS2H

(NOTE)

tODS

tDS

tDH

DATA IN STABLE

READ/WRITE

tWRW

tAS

DON’T CARE

NOTE: tODS is required for common I/O operation only; for separate I/O operations, output disable is “don’t care”.

FIGURE 2. WRITE CYCLE TIME WAVEFORMS

6-60

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