AK4588 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

부품명

상세내역

일치하는 목록

AK4588

2/8-Channel Audio CODEC with DIR

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4588]

(2). I2C bus control mode (I2C pin = “H”)

AK4588 supports the standard-mode I2C-bus (max : 100kHz). Then AK4588 does not support a fast-mode I2C-bus

system (max: 400kHz).

(2)-1. Data transfer

All commands are preceded by a START condition. After the START condition, a slave address is sent. After the

AK4588 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted

over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave

device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition

generated by the master device.

(2)-1-1. Data validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.

SCL

SDA

DATA LINE

STABLE :

DATA VALID

CHANGE

OF DATA

ALLOWED

Figure 41. Data transfer

(2)-1-2. START and STOP condition

A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from

the START condition.

A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the

STOP condition.

SCL

SDA

START CONDITION

STOP CONDITION

Figure 42. START and STOP conditions

MS0287-E-01

- 68 -

2004/03

Share Link: