AK4533 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
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AK4533 Datasheet PDF : 40 Pages
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[ASAHI KASEI]
SWITCHING CHARACHTERISTICS
Ta= -10°C ∼ 70°C, AVdd=DVdd=2.7V ∼ 3.63V, CL=20pF
Parameter
Symbol
min
Typ
Audio
Master Clock Timing
MCLK_SEL=”L” (512fs mode)
MCLK_SEL=”H” (256fs mode)
Pulse Width duty
fMCLK
fMCLK
duty_MCLK
4.096
5.6448
40
50
LRCK Frequency
MCLK_SEL=”L” (fMCLK/512)
MCLK_SEL=”H” (fMCLK/256)
LRCK duty
Serial Interface Timing
SCLK Frequency
SCLK duty
SDI Hold Time after “SCLK rising”
SDI Setup Time for “SCLK rising”
SDO(MSB) delay from “LRCK rising”
SDO delay from “SCLK falling”
LRCK change to “SCLK falling”
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
CCLK Pulse Width High
CDTI Hold Time after “CCLK rising”
CDTI Setup Time for “CCLK rising”
CS Low Level Time (for next command)
“CS rising” to “CCLK rising” time
“CCLK falling” to “CS falling” time
CDTO delay from “CCLK falling”
16CCLK ↓ to CDTO =“L”
Touch Panel (A/D Converter)
Conversion Rate
TADCK
frequency
duty
TADE
“H” Level Period
Setup Time for “TADCLK rising”
Hold Time after “TADCLK rising”
“L” Level Time for next Conversion
Tracking Time
TADOUT delay time from TADCLK ↓
TADRDY
“H” Level Period
TADCK ↓ to TADRDY change
Others
PDB Low Pulse Width
RESETB Low Pulse Width
fs
duty_LRCK
fSCLK
duty_SCLK
tSD_H
tSD_S
tLR_SDO
tSC_SDO
tLR_SCF
tCCK
tCCKL
tCCKH
tCDH
tCDS
tCSW
tCSS
tCSH
tDCD
tCCL
fTADCK
duty_TADCK
tTADES
tTADEH
tTADE_LW
tTRK
tTADD
tRDYD
tPDB
tRESETB
8
22.05
-
50
-
32
40
50
100
-
100
-40
500
200
200
100
100
200
200
0(TBD)
0
0.1
45
50
16
225
225
200
1.5
-
12
200
200
Input signal Rise/fall time (VIL to VIH)
(CS,CCLK,TADE,TADCK, MCLK)
max
Units
11.2896
11.2896
60
22.05
44.1
-
-
60
-
150
150
40
2000
-
100
100
125
2
55
150
-
50
15
MHz
MHz
%
kHz
kHz
%
fs
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
MHz
%
cycle
ns
ns
ns
us
ns
cycle
ns
ns
ns
ns
<Revision 0.9a>
9
July 00
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