AKD4524 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
부품명
상세내역
일치하는 목록
AKD4524 Datasheet PDF : 31 Pages
| |||
ASAHI KASEI
[AK4524]
DIGITAL CHARACTERISTICS
(Ta=25°C; VA, VD=4.75 ∼ 5.25V; VT=2.7 ∼ 5.25V)
Parameter
Symbol
min
typ
High-Level Input Voltage
VIH
2.2
-
Low-Level Input Voltage
VIL
-
-
High-Level Output Voltage (Iout=−100µA) (Note 10) VOH 2.7 / VT−0.5
-
Low-Level Output Voltage (Iout=100µA)
VOL
-
-
Input Leakage Current
Iin
-
-
Note: 10. Min value is lower voltage of 2.7V or VT−0.5V.
Max
Units
-
V
0.8
V
-
V
0.5
V
±10
µA
SWITCHING CHARACTERISTICS
(Ta=25°C; VA, VD=4.75 ∼ 5.25V, VT=2.7 ∼ 5.25V; CL=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Crystal Resonator Frequency
11.2896
External Clock
Frequency
fCLK
8.192
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High tCLKH 0.4/fCLK
CLKO Output
Frequency
fMCK 11.2896
(X’tal mode)
Duty Cycle
dMCK
35
LRCK Frequency
Normal Speed Mode (DFS0=“0”, DFS1=“0”)
fsn
32
Double Speed Mode (DFS0=“1”, DFS1=“0”)
fsd
64
Quad Speed Mode (DFS0=“0”, DFS1=“1”)
fsq
128
Duty Cycle
Slave mode
45
Master mode
50
Audio Interface Timing
Slave mode
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
33
Pulse Width High
tBCKH
33
LRCK Edge to BICK “↑”
(Note 11) tLRB
20
BICK “↑” to LRCK Edge
(Note 11) tBLR
20
LRCK to SDTO (MSB) (Except I2S mode) tLRS
BICK “↓” to SDTO
tBSD
SDTI Hold Time
tSDH
20
SDTI Setup Time
tSDS
20
Master mode
BICK Frequency
fBCK
64fs
BICK Duty
dBCK
50
BICK “↓” to LRCK
BICK “↓” to SDTO
tMBLR
-20
tBSD
-20
SDTI Hold Time
tSDH
20
SDTI Setup Time
tSDS
20
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
max
24.576
49.152
24.576
65
48
96
192
55
Units
MHz
MHz
ns
ns
MHz
%
kHz
kHz
kHz
%
%
ns
ns
ns
ns
ns
40
ns
40
ns
ns
ns
Hz
%
20
ns
20
ns
ns
ns
M0050-E-03
-8-
2004/01
Share Link: 