AK4386(2003) 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
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AK4386 Datasheet PDF : 16 Pages
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ASAHI KASEI
[AK4386]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.2 ∼ 3.6V)
Parameter
Symbol
min
typ
Master Clock Frequency
Half Speed Mode (512/768/1024/1536fs)
fCLK
4.096
Normal Speed Mode (256/384/512/768fs)
fCLK
2.048
Double Speed Mode (128/192/256/384fs)
fCLK
6.144
Duty Cycle
dCLK
40
LRCK Frequency
Half Speed Mode (DFS1-0 = “10”)
fsh
8
Normal Speed Mode (DFS1-0 = “00”)
fsn
8
Double Speed Mode (DFS1-0 = “01”)
fsd
48
Duty Cycle
dCLK
45
Audio Interface Timing
BICK Period
Half Speed Mode
tBCK
1/128fs
Normal Speed Mode
tBCK
1/128fs
Double Speed Mode
tBCK
1/64fs
BICK Pulse Width Low
tBCKL
70
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
tBCKH
70
(Note 8) tBLR
40
(Note 8) tLRB
40
SDTI Hold Time
tSDH
40
SDTI Setup Time
tSDS
40
Power-Down & Reset Timing
PDN Pulse Width
(Note 9) tPD
4×C
max
36.864
36.864
36.864
60
24
48
96
55
Units
MHz
MHz
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
Note 9. The AK4386 can be reset by bringing PDN pin = “L”.
The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4 × C.
When C = 4.7µF, tPD is 19ms(min).
The value of the capacitor (C) connected with VCOM pin should be 1µF ≤ C ≤ 10µF.
When the states of DIF1-0 pins change, the AK4386 should be reset by PDN pin.
MS0280-E-00
-7-
2003/12
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