AKD4365 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
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AKD4365 Datasheet PDF : 38 Pages
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ASAHI KASEI
[AK4365]
PIN/FUNCTION
No. Pin Name
1 CS
2 CDTI
3 CCLK
4 LRCK
5 BICK
6 SDATA
7 DVDD
8 DGND
9 MCKI
10 RSTN
11 SMODE
12 MIN
13 LIN
14 RIN
15 AGND
16 AVDD
17 VREF
18 VCOM
19 MUTET
20 HPVCC
21 HPGND
22 HPR
23 HPL
24 MOUT
25 PLLGND
26 VCOC
27 PLLVCC
28 MCKO
I/O
Function
I Control Data Chip Select Pin
I Control Data Input Pin
I Control Clock Input Pin
L/R Clock Pin
I/O
This clock determines which audio channel is currently being input on SDATA pin.
When SMODE pin = “L”, a clock with fs rate is output. This pin is fixed to “L” at
power-down. When SMODE pin = “H”, a L/R clock is input.
Serial Bit Clock Pin
I/O
This clock is used to latch audio data. When SMODE pin = “L”, a clock with 32fs or
64fs rate is output. This pin is fixed to “L” at power-down. When SMODE pin = “H”, a
bit clock is input.
I Audio Data Input Pin
- Digital Power Supply Pin
- Digital Ground Pin
I Master Clock Input Pin
Reset Pin
I When at “L”, the AK4365 is in power-down mode and is held in reset.
The AK4365 should always be reset upon power-up.
I
Master/Slave Mode Select Pin
“L”: Master Mode, “H”: Slave Mode
I Mono Analog Input Pin
I Lch Analog Input Pin
I Rch Analog Input Pin
- Analog Ground Pin
- Analog Power Supply Pin
Reference Voltage Output Pin, 2.0V (typ, respect to AGND)
O Normally connected to AGND pin with 0.1µF ceramic capacitor in parallel with a 10µF
electrolytic capacitor.
Common Voltage Output Pin, 1.0V (typ, respect to AGND)
O Normally connected to AGND pin with 0.1µF ceramic capacitor in parallel with a 1µF
electrolytic capacitor.
O
Mute Time Constant Control Pin
Connected to AGND pin with a capacitor for mute time constant.
- Power Supply Pin for Headphone Amplifier
- Ground Pin for Headphone Amplifier
O Rch Headphone Amplifier Output Pin
O Lch Headphone Amplifier Output Pin
O Monaural Analog Output Pin
- Ground Pin for PLL. Connected to AGND.
O
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to AGND with one resistor and one capacitor in series.
- Power Supply Pin for PLL. Normally connected to AVDD.
O Master Clock Output Pin
Note: All digital input pins must not be left floating.
MS0110-E-01
-4-
2003/10
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