AK4357 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
부품명
상세내역
일치하는 목록
AK4357 Datasheet PDF : 27 Pages
| |||
ASAHI KASEI
[AK4357]
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896MHz
12.2880MHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
fs
176.4kHz
192.0kHz
MCLK
128fs
192fs
22.5792MHz 33.8688MHz
24.5760MHz 36.8640MHz
BICK
64fs
11.2896MHz
12.2880MHz
Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
512fs
768fs
256fs
384fs
128fs
192fs
Sampling Speed
Normal
Double
Quad
Table 6. Sampling Speed (Auto Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
-
-
-
-
-
22.5792
24.5760
192fs
-
-
-
-
-
33.8688
36.8640
MCLK (MHz)
256fs
384fs
-
-
-
-
-
-
22.5792 33.8688
24.5760 36.8640
-
-
-
-
512fs
16.3840
22.5792
24.5760
-
-
-
-
768fs
24.5760
33.8688
36.8640
-
-
-
-
Sampling Speed
Normal
Double
Quad
Table 7. System Clock Example (Auto Setting Mode)
2) DSD Mode
The external clocks, which are required to operate the AK4357, are MCLK and DCLK. The master clock (MCLK) should be
synchronized with DSD clock (DCLK) but the phase is not critic al. The frequency of MCLK is set by DCKS bit.
All external clocks (MCLK, DCLK) should always be present whenever the AK4357 is in the normal operation mode
(PDN= ”H”). If these clocks are not provided, the AK4357 may draw excess current because the device utilizes dynamic
refreshed logic internally. The AK4357 should be reset by PDN= ”L” after threse clocks are provided. If the external clocks
are not present, the AK4357 should be in the power-down mode (PDN= ”L”). After exiting reset(PDN = “↑”) at power-up
etc., the AK4357 is in the power-down mode until MCLK is input. PCM interface signals (BICK, LRCK, SDTI1 -3) are fixed to
“H” or “L”.
DCKS
MCLK
DCLK
0
512fs
64fs
1
768fs
64fs
Table 8. System Clock (fs=44.1kHz)
MS0088-E-02
- 11 -
2002/07
Share Link: 