CY7C4201V-10AC 데이터 시트보기 (PDF) - Cypress Semiconductor

부품명

상세내역

일치하는 목록

CY7C4201V-10AC

Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Full Flag Timing

NO WRITE

WCLK

D0 –D8

tSKEW1 [11]

tWFF

FF

NO WRITE

tDS

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

NO WRITE

tSKEW1 [11]

DATA WRITE

tWFF

tWFF

DATA WRITE

WEN1

WEN2

(if applicable)

RCLK

REN1,

REN2

tENS

tENH

OE

Q0 –Q8

LOW

tA

DATA IN OUTPUT REGISTER

tENS

tENH

DATA READ

tA

NEXT DATA READ

Programmable Almost Empty Flag Timing

tCLKH

tCLKL

WCLK

WEN1

tENS tENH

WEN2

(if applicable)

PAE

RCLK

tENS tENH

Note 19

tSKEW2 [18]

tPAE

N + 1 WORDS

INFIFO

Note 20

tPAE

tENS

tENS tENH

REN1,

REN2

Notes:

18. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising

RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.

19. PAE offset = n.

20. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.

Document #: 38-06010 Rev. *A

Page 13 of 17

Share Link: