AK2307LV 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AK2307LV

SPEECH CODEC for Digital Key telephone (5.0V/3.3V)

Asahi Kasei Microdevices 

ASAHI KASEI

FUNCTIONAL DISCRIPTIONS

[AK2307/LV]

1. SERIAL INTERFACE

The internal registers can be read/written via serial CPU interface which consists of SCLK, DATA, and CSN

pin.

1 word consists of 16bits. The first 3bits are the instruction code which specifies read or write.

The following 4bits specify the address. The rest of 8bits are the data stored in the internal registers.

Table1-A CPU I/F ADDRESS/DATA STRUCTURE

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

I2 I1 I0 A3 A2 A1 A0 * D7 D6 D5 D4 D3 D2 D1 D0

Instruction code

(3 bit )

Address

(4bit)

*

*)Dummy bit for adjusting the I/O timing when reading register.

Table1-B INSTRUCTION CODE

I2

I1

I0

1

1

0

1

1

1

Others

Data for internal registers

(8bit)

Read/Write

Read

Write

No action

1-2 Timing of the Serial Interface

SCLK and DATA timing in WRITE/READ operation

(1) Input data are loaded into the internal shift register at the rising edge of SCLK.

(2) The rising edge of SCLK is counted after the falling edge of CSN.

(3) When CSN is “L” and more than 16 SCLK pulses:

[WRITE] Data are loaded into the internal register at the rising edge of the SCLK 16th pulse.

[READ] DATA pin becomes an input pin at the falling edge of the SCLK 16th pulse.

CSN timing and WRITE/READ CANCELLATION

(1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16th pulse.

(2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16th pulse.

SERIAL WRITE/READ ACCESS timing (SERIAL ACCESS MODE)

(1) Serial write and read operation will be done by feeding the another 16 SCLK pulse and

data after 1st write or read operation.

(2) It is not necessary to make CSN high between 1st operation and 2nd operation.

MS0190-E-05

6

2005/12

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