AIC1341 데이터 시트보기 (PDF) - Analog Intergrations
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AIC1341 Datasheet PDF : 14 Pages
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Shutdown
Compatible with the TTL logic level, by holding the
SD (pin3) pin low will activate the controller. If
connecting a resistor to ground, make sure the
resistor is less than 4.7KΩ for normal operation.
Layout Considerations
Any inductance in the switched current path gen-
erates a large voltage spike during the switching
interval. The voltage spikes can degrade efficiency,
radiate noise into the circuit, and lead to device
over-voltage stress. Careful component selection
and tight layout of critical components, and short,
wide metal trace minimize the voltage spike.
1) A ground plane should be used. Locate the
input capacitors (CIN) close to the power
switches. Minimize the loop formed by CIN,
the upper MOSFET (Q1) and the lower
MOSFET (Q2) as possible. Connections
should be as wide as short as possible to
minimize loop inductance.
2) The connection between Q1, Q2 and output
inductor should be as wide as short as practi-
cal. Since this connection has fast voltage
transitions will easily induce EMI.
3) The output capacitor (COUT) should be locat-
ed as close the load as possible. Because
minimize the transient load magnitude for high
slew rate requires low inductance and resis-
tance in circuit board
4) The AIC1341 is best placed over a quiet
ground plane area. The GND pin should be
connected to the groundside of the output ca-
pacitors. Under no circumstances should
GND be returned to a ground inside the CIN,
AIC1341
Q1, Q2 loop. The GND and PGND pins
should be shorted right at the IC. This help to
minimize internal ground disturbances in the
IC and prevents differences in ground potential
from disrupting internal circuit operation.
5) The wiring traces from the control IC to the
MOSFET gate and source should be sized to
carry 1A current. Locate COUT2 close to the
AIC1341 IC.
6) The Vcc pin should be decoupled directly to
GND by a 1µF ceramic capacitor, trace
lengths should be as short as possible.
A multi-layer printed circuit board is recom-
mended. Figure 6 shows the connections of the
critical components in the converter. The CIN and
COUT could each represent numerous physical ca-
pacitors. Dedicate one solid layer for a ground
plane and make all critical component ground
connections with vias to this layer.
PWM Output Capacitors
The load transient for the microprocessor core re-
quires high quality capacitors to supply the high
slew rate (di/dt) current demand.
The ESR (equivalent series resistance) and ESL
(equivalent series inductance) parameters rather
than actual capacitance determine the buck ca-
pacitor values. For a given transient load magni-
tude, the output voltage transient change due to
the output capacitor can be note by the following
equation:
∆VOUT = ESR × ∆IOUT + ESL × ∆IOUT ,
∆T
∆IOUT is transient load current step.
where
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